Simulation Results: otp_ctrl

 
12/04/2026 00:11:27 DVSim: v1.29.0 sha: 4a305de json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.73 %
  • code
  • 85.29 %
  • assert
  • 94.75 %
  • func
  • 92.16 %
  • line
  • 90.25 %
  • branch
  • 85.53 %
  • cond
  • 91.72 %
  • toggle
  • 96.11 %
  • FSM
  • 62.85 %
Validation stages
V1
95.69%
V2
91.25%
V2S
89.16%
V3
0.99%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.730s 202.858us 1 1 100.00
smoke 50 50 100.00
otp_ctrl_smoke 21.080s 3111.259us 50 50 100.00
csr_hw_reset 5 5 100.00
otp_ctrl_csr_hw_reset 2.160s 407.999us 5 5 100.00
csr_rw 20 20 100.00
otp_ctrl_csr_rw 3.010s 535.553us 20 20 100.00
csr_bit_bash 5 5 100.00
otp_ctrl_csr_bit_bash 8.450s 842.297us 5 5 100.00
csr_aliasing 5 5 100.00
otp_ctrl_csr_aliasing 5.580s 763.923us 5 5 100.00
csr_mem_rw_with_rand_reset 15 20 75.00
otp_ctrl_csr_mem_rw_with_rand_reset 4.280s 1592.504us 15 20 75.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
otp_ctrl_csr_rw 3.010s 535.553us 20 20 100.00
otp_ctrl_csr_aliasing 5.580s 763.923us 5 5 100.00
mem_walk 5 5 100.00
otp_ctrl_mem_walk 1.790s 117.756us 5 5 100.00
mem_partial_access 5 5 100.00
otp_ctrl_mem_partial_access 1.790s 569.635us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 15.440s 1607.341us 1 1 100.00
init_fail 285 300 95.00
otp_ctrl_init_fail 6.540s 2184.900us 285 300 95.00
partition_check 21 60 35.00
otp_ctrl_background_chks 32.930s 14962.343us 7 10 70.00
otp_ctrl_check_fail 28.360s 5920.568us 14 50 28.00
regwen_during_otp_init 50 50 100.00
otp_ctrl_regwen 13.740s 4372.955us 50 50 100.00
partition_lock 50 50 100.00
otp_ctrl_dai_lock 33.430s 3658.010us 50 50 100.00
interface_key_check 50 50 100.00
otp_ctrl_parallel_key_req 25.710s 1544.963us 50 50 100.00
lc_interactions 250 250 100.00
otp_ctrl_parallel_lc_req 25.500s 9626.375us 50 50 100.00
otp_ctrl_parallel_lc_esc 26.850s 11338.350us 200 200 100.00
otp_dai_errors 48 50 96.00
otp_ctrl_dai_errs 29.290s 4589.824us 48 50 96.00
otp_macro_errors 19 50 38.00
otp_ctrl_macro_errs 17.450s 2171.574us 19 50 38.00
test_access 50 50 100.00
otp_ctrl_test_access 42.380s 7660.205us 50 50 100.00
stress_all 38 50 76.00
otp_ctrl_stress_all 1095.330s 124209.681us 38 50 76.00
intr_test 50 50 100.00
otp_ctrl_intr_test 2.340s 621.441us 50 50 100.00
alert_test 50 50 100.00
otp_ctrl_alert_test 3.930s 285.403us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
otp_ctrl_tl_errors 8.490s 2705.314us 20 20 100.00
tl_d_illegal_access 20 20 100.00
otp_ctrl_tl_errors 8.490s 2705.314us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
otp_ctrl_csr_hw_reset 2.160s 407.999us 5 5 100.00
otp_ctrl_csr_rw 3.010s 535.553us 20 20 100.00
otp_ctrl_csr_aliasing 5.580s 763.923us 5 5 100.00
otp_ctrl_same_csr_outstanding 4.570s 1857.508us 20 20 100.00
tl_d_partial_access 50 50 100.00
otp_ctrl_csr_hw_reset 2.160s 407.999us 5 5 100.00
otp_ctrl_csr_rw 3.010s 535.553us 20 20 100.00
otp_ctrl_csr_aliasing 5.580s 763.923us 5 5 100.00
otp_ctrl_same_csr_outstanding 4.570s 1857.508us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 3 5 60.00
otp_ctrl_sec_cm 154.430s 41667.759us 3 5 60.00
tl_intg_err 23 25 92.00
otp_ctrl_sec_cm 154.430s 41667.759us 3 5 60.00
otp_ctrl_tl_intg_err 42.900s 19030.699us 20 20 100.00
prim_count_check 3 5 60.00
otp_ctrl_sec_cm 154.430s 41667.759us 3 5 60.00
prim_fsm_check 3 5 60.00
otp_ctrl_sec_cm 154.430s 41667.759us 3 5 60.00
sec_cm_bus_integrity 20 20 100.00
otp_ctrl_tl_intg_err 42.900s 19030.699us 20 20 100.00
sec_cm_secret_mem_scramble 50 50 100.00
otp_ctrl_smoke 21.080s 3111.259us 50 50 100.00
sec_cm_part_mem_digest 50 50 100.00
otp_ctrl_smoke 21.080s 3111.259us 50 50 100.00
sec_cm_dai_fsm_sparse 3 5 60.00
otp_ctrl_sec_cm 154.430s 41667.759us 3 5 60.00
sec_cm_kdi_fsm_sparse 3 5 60.00
otp_ctrl_sec_cm 154.430s 41667.759us 3 5 60.00
sec_cm_lci_fsm_sparse 3 5 60.00
otp_ctrl_sec_cm 154.430s 41667.759us 3 5 60.00
sec_cm_part_fsm_sparse 3 5 60.00
otp_ctrl_sec_cm 154.430s 41667.759us 3 5 60.00
sec_cm_scrmbl_fsm_sparse 3 5 60.00
otp_ctrl_sec_cm 154.430s 41667.759us 3 5 60.00
sec_cm_timer_fsm_sparse 3 5 60.00
otp_ctrl_sec_cm 154.430s 41667.759us 3 5 60.00
sec_cm_dai_ctr_redun 3 5 60.00
otp_ctrl_sec_cm 154.430s 41667.759us 3 5 60.00
sec_cm_kdi_seed_ctr_redun 3 5 60.00
otp_ctrl_sec_cm 154.430s 41667.759us 3 5 60.00
sec_cm_kdi_entropy_ctr_redun 3 5 60.00
otp_ctrl_sec_cm 154.430s 41667.759us 3 5 60.00
sec_cm_lci_ctr_redun 3 5 60.00
otp_ctrl_sec_cm 154.430s 41667.759us 3 5 60.00
sec_cm_part_ctr_redun 3 5 60.00
otp_ctrl_sec_cm 154.430s 41667.759us 3 5 60.00
sec_cm_scrmbl_ctr_redun 3 5 60.00
otp_ctrl_sec_cm 154.430s 41667.759us 3 5 60.00
sec_cm_timer_integ_ctr_redun 3 5 60.00
otp_ctrl_sec_cm 154.430s 41667.759us 3 5 60.00
sec_cm_timer_cnsty_ctr_redun 3 5 60.00
otp_ctrl_sec_cm 154.430s 41667.759us 3 5 60.00
sec_cm_timer_lfsr_redun 3 5 60.00
otp_ctrl_sec_cm 154.430s 41667.759us 3 5 60.00
sec_cm_dai_fsm_local_esc 203 205 99.02
otp_ctrl_parallel_lc_esc 26.850s 11338.350us 200 200 100.00
otp_ctrl_sec_cm 154.430s 41667.759us 3 5 60.00
sec_cm_lci_fsm_local_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 26.850s 11338.350us 200 200 100.00
sec_cm_kdi_fsm_local_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 26.850s 11338.350us 200 200 100.00
sec_cm_part_fsm_local_esc 219 250 87.60
otp_ctrl_parallel_lc_esc 26.850s 11338.350us 200 200 100.00
otp_ctrl_macro_errs 17.450s 2171.574us 19 50 38.00
sec_cm_scrmbl_fsm_local_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 26.850s 11338.350us 200 200 100.00
sec_cm_timer_fsm_local_esc 203 205 99.02
otp_ctrl_parallel_lc_esc 26.850s 11338.350us 200 200 100.00
otp_ctrl_sec_cm 154.430s 41667.759us 3 5 60.00
sec_cm_dai_fsm_global_esc 203 205 99.02
otp_ctrl_parallel_lc_esc 26.850s 11338.350us 200 200 100.00
otp_ctrl_sec_cm 154.430s 41667.759us 3 5 60.00
sec_cm_lci_fsm_global_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 26.850s 11338.350us 200 200 100.00
sec_cm_kdi_fsm_global_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 26.850s 11338.350us 200 200 100.00
sec_cm_part_fsm_global_esc 219 250 87.60
otp_ctrl_parallel_lc_esc 26.850s 11338.350us 200 200 100.00
otp_ctrl_macro_errs 17.450s 2171.574us 19 50 38.00
sec_cm_scrmbl_fsm_global_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 26.850s 11338.350us 200 200 100.00
sec_cm_timer_fsm_global_esc 203 205 99.02
otp_ctrl_parallel_lc_esc 26.850s 11338.350us 200 200 100.00
otp_ctrl_sec_cm 154.430s 41667.759us 3 5 60.00
sec_cm_part_data_reg_integrity 285 300 95.00
otp_ctrl_init_fail 6.540s 2184.900us 285 300 95.00
sec_cm_part_data_reg_bkgn_chk 14 50 28.00
otp_ctrl_check_fail 28.360s 5920.568us 14 50 28.00
sec_cm_part_mem_regren 50 50 100.00
otp_ctrl_dai_lock 33.430s 3658.010us 50 50 100.00
sec_cm_part_mem_sw_unreadable 50 50 100.00
otp_ctrl_dai_lock 33.430s 3658.010us 50 50 100.00
sec_cm_part_mem_sw_unwritable 50 50 100.00
otp_ctrl_dai_lock 33.430s 3658.010us 50 50 100.00
sec_cm_lc_part_mem_sw_noaccess 50 50 100.00
otp_ctrl_dai_lock 33.430s 3658.010us 50 50 100.00
sec_cm_access_ctrl_mubi 50 50 100.00
otp_ctrl_dai_lock 33.430s 3658.010us 50 50 100.00
sec_cm_token_valid_ctrl_mubi 50 50 100.00
otp_ctrl_smoke 21.080s 3111.259us 50 50 100.00
sec_cm_lc_ctrl_intersig_mubi 50 50 100.00
otp_ctrl_dai_lock 33.430s 3658.010us 50 50 100.00
sec_cm_test_bus_lc_gated 50 50 100.00
otp_ctrl_smoke 21.080s 3111.259us 50 50 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 3 5 60.00
otp_ctrl_sec_cm 154.430s 41667.759us 3 5 60.00
sec_cm_direct_access_config_regwen 50 50 100.00
otp_ctrl_regwen 13.740s 4372.955us 50 50 100.00
sec_cm_check_trigger_config_regwen 50 50 100.00
otp_ctrl_smoke 21.080s 3111.259us 50 50 100.00
sec_cm_check_config_regwen 50 50 100.00
otp_ctrl_smoke 21.080s 3111.259us 50 50 100.00
sec_cm_macro_mem_integrity 19 50 38.00
otp_ctrl_macro_errs 17.450s 2171.574us 19 50 38.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 13.520s 3362.918us 1 1 100.00
stress_all_with_rand_reset 0 100 0.00
otp_ctrl_stress_all_with_rand_reset 31.440s 3842.045us 0 100 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_*
otp_ctrl_macro_errs 34750692430270822593388103389550508972791176870753526699403607989089389626841 677
UVM_INFO @ 115737562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 71772090217235347590857223927955898598407417326017208157026312234700102038593 5158
UVM_INFO @ 534577955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 44186090784519636350678951368855018259102457157453663303190951457426248603713 1290
UVM_INFO @ 716549394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 44231680773828490003300157274012997164244163234085774935924126741235623625085 5959
UVM_INFO @ 1852601699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 594770842604855029997155644539103248588311872702684566404162763133507426433 2663
UVM_INFO @ 311244685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 84886746480996524443968135450714971193242584987165030859168223833342300466397 4798
UVM_INFO @ 287105844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 56490492132155415967284616747952758952169648922654854859765080271182159399603 3927
UVM_INFO @ 622696963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 3832012481800222127638034846387458632158482235520620090335424470648232252819 578
UVM_INFO @ 83322143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 90659622071564025707768040257298967320440796836937081652693181606373970426097 1265
UVM_INFO @ 78359939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 110861431780683035419330020703177256471558559726707341512158077725270522153827 6221
UVM_INFO @ 529300462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 23827147817939408656791107855592425846046222681426557870872269902923352806416 17970
UVM_INFO @ 4629064090 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 113474358751341141333982240192825445014794283558425172338470703981386212759663 14870
UVM_INFO @ 19424451907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 15729345542698306070363130504444011875155472420651796068099432435819297446108 3582
UVM_INFO @ 529514669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 19697382685315380845167333455912791812051380016555645139954458397082367063758 5533
UVM_INFO @ 1111719505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 58763125269551390191256165070060524534313033783984204401030657283060048739154 4538
UVM_INFO @ 683337142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 36612170527509753513038979149364415088314015437753264243704966991250722972585 407
UVM_INFO @ 390319955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 8148246580402010426894493977471506186157181484059122876099340222903211559160 5784
UVM_INFO @ 420630057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 110470729432339855534554821251195481852561913575083834688381627199933257841419 1345
UVM_INFO @ 227624625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 115377608636215866390185183300911417314581249517223116017517131879412477644448 4456
UVM_INFO @ 493344250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 15150956058135649527374691778111150825117007997947323186179051371616781130827 4608
UVM_INFO @ 308447351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 61911607927546023464192834008926494820781526747344110913587702896435342361194 2094
UVM_INFO @ 173729040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 43502627500295989939963653258882366230330138329961582357443772199566502615350 621
UVM_INFO @ 758634967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 98431213425406835487659123126654179577850034735586752636196907931041457522560 5284
UVM_INFO @ 648194561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 72301794874236974067048575111930412475749900230962871084026420347263842552043 3462
UVM_INFO @ 145058684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 41245115933638175434678591508661464461536796568026786143041645644313570073658 647
UVM_INFO @ 88041944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 91931567761578462072488618352494943328992719663064700797096700131384813973152 1043
UVM_INFO @ 1335282836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 76482569507557207366122336822795435686591692797146811302190073722396866353125 1920
UVM_INFO @ 719435131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 93675545234313217051564118359258051260111701468897468305949821220274158088418 7389
UVM_INFO @ 1196463181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 72645847103550396569294516739344648583319580777939105985421908480955101061253 705
UVM_INFO @ 183145987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 65357324519916612600934412424554339766733357371599833238551486064077836384430 215
UVM_INFO @ 61944407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 78362245635843078199097427613852174125845723390884379474773753760987906191435 12900
UVM_INFO @ 1785318138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 13479681402887706385662066186560503742616303893105574515973157609089448562525 1103
UVM_INFO @ 403197851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 99554441645878473885806106219968245984138838201202457109014425696485720643273 1967
UVM_INFO @ 334850785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 16062480644717494229209110390350855979783117091986180369328751729897675736620 444
UVM_INFO @ 844481235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 90445919480273580780235885436335861350425384852112785512759156993343187848038 2546
UVM_INFO @ 833991243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 11546811859488702855550121177172926931433084794449432123497859764391919657499 1725
UVM_INFO @ 192124835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 13147645900583295947613193365698060585440499352377604089515629937311789600822 2135
UVM_INFO @ 247693528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 73472970157686682789812059978919376432077862100217688752817992752881062935902 6423
UVM_INFO @ 1701147408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 110887640032761668779659493884075402331522478266379574261166956547171330211161 5924
UVM_INFO @ 2254437124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 113460159696005252779202326558711566289590346462142709196172825629858753467502 1043
UVM_INFO @ 71968160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 111003866283307322493654061431638825289871871225575004359761666968150109921410 4549
UVM_INFO @ 1333982042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 43142333876403550379714192013143647534592069544179866001708059072217604097967 8784
UVM_INFO @ 1124841879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 86291521053671112286578529063515065643981691724159295622445471265257757242574 413
UVM_INFO @ 140940061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 24077400227603467537064300374972717063976831778159350944788501467905426405506 4169
UVM_INFO @ 1054099787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 88522244048909550735755235385231521517317810179718639448427826582317993263819 5897
UVM_INFO @ 237632878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 875641178326956931671086733969660384509000825309659188480287675533271090096 1107
UVM_INFO @ 3447391136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 97013522773524939507172073368719217019941039251963794436342369612718820901740 9891
UVM_INFO @ 1846499771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 113335681337957706513045292146523123095842446199057329192708594702798893301602 4849
UVM_INFO @ 727477666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 8682165054488522666209489258545020210262551957251620887711144014873437143326 5628
UVM_INFO @ 1367199876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 85373884474229773388811884692232890280582024605311660455996725876382514944675 5608
UVM_INFO @ 1711081142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 101321327037517139571696956512345079785481825139447806223461746217638539924836 931
UVM_INFO @ 203137445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 72618168454093303247146315326104957150844879485429345408543693957157396705674 1973
UVM_INFO @ 93042647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 88656983962909272521939676312864330362971078540300852293620932251920034043103 6094
UVM_INFO @ 322368377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 19861328977520308934104118123274636944098463634132745780915159442978796394884 5376
UVM_INFO @ 983499484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 15572372691964143030316432997338464328939436262043806656564648292957878232505 4798
UVM_INFO @ 968140427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 28091115209191331230310143398897407996280870272396073846957550779018373528277 165
UVM_INFO @ 33472583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 44774397974432515582493280052248185469623871353626682794433435342290805835406 2995
UVM_INFO @ 1387963606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 56566377282816350676154435912720018982785450403184944931135120933405365155698 943
UVM_INFO @ 236487746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 28203006811680789616381316186026766695013247709926361640609428038302156629862 2803
UVM_INFO @ 754596204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 46295958576908175762033425000350515208552655027002370893923452031757810655498 6389
UVM_INFO @ 1439007149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 46052388561153579715976010834501227526712482381040010535801772237787906177764 3238
UVM_INFO @ 4445602676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 98147517576301501449310627695132854378505386603932254391155000983702786134825 2009
UVM_INFO @ 240978695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 73275054496840305549767772898890857852524516444157514493545599615017653635521 4244
UVM_INFO @ 2792900281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = *
otp_ctrl_stress_all_with_rand_reset 66594615657792623957672588587368787531643273595353578514880190077724380154653 95
UVM_INFO @ 54350351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 95080544827670774824760957318201726781885733212364995064818266061364821689494 93
UVM_INFO @ 51876333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_csr_mem_rw_with_rand_reset 46099000357671899510151959019323462498904188693834811251766273106378856669935 92
UVM_INFO @ 435390907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 79768158521313152826214714765874731556870347222950818977898030679058956170921 238
UVM_INFO @ 421958253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 66119150338124643012381667505728894740425026178502092378931259357703714244822 92
UVM_INFO @ 55111440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 3040659241901458353780661178907307043389522622162296902318713239865700511713 217
UVM_INFO @ 263522622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 80465015970094126548895468737971765558760371185249033200004654891722307865091 92
UVM_INFO @ 88078097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 3171733871241224946954117541281571829584985627463342188672949472053049277034 529
UVM_INFO @ 1200752955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 54768077992676025942641900860176011927684298938961034403807513120445976167340 99
UVM_INFO @ 441966969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 85434278979107980878198958593429091427240979776263573580504239348594618811742 96
UVM_INFO @ 54788978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 85091810624975654696123159628086269096214894059032634061653977494895671002048 1720
UVM_INFO @ 421442771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_csr_mem_rw_with_rand_reset 98725938276345227280651081733218431936669912113554942524614617255065165348831 92
UVM_INFO @ 432098655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 112756029045081487149854470606812442492571102196051034566707769247589518290184 93
UVM_INFO @ 107800387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 107095403345507496262734946816384648453231754838908420263151521963681482930835 93
UVM_INFO @ 433092114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 51863091242111854818854243525035262294355689447508005079738511522939208223550 99
UVM_INFO @ 457837466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_csr_mem_rw_with_rand_reset 13683941692123692853494708833186306367834178092033521203001870510694701334302 98
UVM_INFO @ 64406196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 114236420262677949341279656731521005569098847371218363494422168551416190779152 92
UVM_INFO @ 510114791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 61991354876262338246361642157900651171441488659081237146473555070611253716584 93
UVM_INFO @ 430688862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 19703413630233143688086481897861247507033577561716472410300695076529012872550 93
UVM_INFO @ 27069367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 85467813299387762892874563001766670222570077009352446634967787219373090774427 93
UVM_INFO @ 440398289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_csr_mem_rw_with_rand_reset 74588601067488119043051298678199038411580273707905305467068828835215389077869 92
UVM_INFO @ 33047168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 50653037952262671113327256216048986496890462286209156471122945527306825110315 92
UVM_INFO @ 106910121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 109305867236074148887433088160347983698528592976492108641355509617042390157566 95
UVM_INFO @ 52747384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_csr_mem_rw_with_rand_reset 3053184350381394696514854805049621786279120051569033332543889661635224717813 92
UVM_INFO @ 107750544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 48095930625779730544304637770960270972898772897874987420982970595042540229790 92
UVM_INFO @ 28488162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 110293991549578120045788698394574518011409403052860866028971280340019508535278 153
UVM_INFO @ 124581222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 97006136457790391601601180976552806831459030423616992888663742849691646600469 98
UVM_INFO @ 58488912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 82879061681700530906111690713276910259436971384301867958628098439744148393194 94
UVM_INFO @ 55691157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 84971325117044884343859476931989512504010663457622881989688714928738462006237 105
UVM_INFO @ 27041151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 108726589845976311724250400820345756037671891590828293082632398913902364447171 94
UVM_INFO @ 54497127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 73708988983738701728023356061820991720645835975851358647020914668670312308979 92
UVM_INFO @ 29127453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 39349412107874444487013327935688031735768899433157368294178062576332575962050 95
UVM_INFO @ 115829972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 110632064593166092913307367495860617113254410993607346855259929416216780290295 92
UVM_INFO @ 57010010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 20339244828758276534874855566719243771982444579991207769265599429701279381166 92
UVM_INFO @ 53206386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 59239535791696649944194725242280449279883769076744511882046513418416698039485 95
UVM_INFO @ 428355202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 85213345246690648452986174131429784506632206783630212508310656624911454954676 92
UVM_INFO @ 29565013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 86679048347168939463409760865904445479625390694093562621082432070658111583199 95
UVM_INFO @ 55054274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 60183905835231759766327758841827442922845792261832578053999277010219828827655 92
UVM_INFO @ 109371987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 25426780573796919736835952046295075003160926486252563824989179164674557332462 97
UVM_INFO @ 52755271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 75850561256975734016701642625608689728783447793784300762785630835701202271014 95
UVM_INFO @ 36480891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 80981828483102792481129113107685951892385547607724360142021979315768283242212 271
UVM_INFO @ 389415529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 95077236502800199291831048725875852834952258663968541790813963073399428268481 107
UVM_INFO @ 435926566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 90250385471107499487811936479481574909949044090267826321273946094225980883104 101
UVM_INFO @ 26990074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 38374561430641989755721454334042898710482709518977758097848669361009034189744 107
UVM_INFO @ 56218571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 70018381798412362164899830443041291924569468852073837421962663543076908840536 93
UVM_INFO @ 107571536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 81053321404204471286229683090768290900494116368659347140979577954039804462400 93
UVM_INFO @ 42891651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 85229122729606608159222490694473703530707293374226546451365843916205957278151 101
UVM_INFO @ 55196146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 94395050011325067725362282227274050423063575757351392275756926759857478140619 103
UVM_INFO @ 447067675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 2776304568849279809672071719090756558234532078428048413669060131173674933822 93
UVM_INFO @ 432732553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 107865165805433441371762588909345585654723613205245258580483927379774710490991 93
UVM_INFO @ 430982791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 33007706086740822006180352629759107896118014453411268180239472266710371203420 92
UVM_INFO @ 29023251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 77326511707034412163954606992425398364500386461202909660921654349713660951568 94
UVM_INFO @ 26898928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 93830888407672166069823457452349856170737079023132811042084764181412713535015 97
UVM_INFO @ 66237681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 96107630084005420952655172523521522048087093607550115229277226974062916022133 95
UVM_INFO @ 104158795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 16225980348162344980395047473713458000708383150435000236761355217886257189716 113
UVM_INFO @ 34104260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 31068687028875875508558365140191146683464515469776589997181220128674699879598 11852
UVM_INFO @ 3842044950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 6232741904525042099575466821894271062125296957917972170918526251653206960404 93
UVM_INFO @ 52732899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 54828634658234818730142682793422625168007975235293845303143820569258847986450 120
UVM_INFO @ 131086032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 35149166415009928579931745939876687346210395441103102388684122751258460611495 93
UVM_INFO @ 26740029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 80540551712246847234030681615098427082612437324011834964035674574888263701668 97
UVM_INFO @ 437701127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 79178967319682680428561701168678355776404176169272609884984697544900200731199 3120
UVM_INFO @ 9913881258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 32202671142111521353243853016723917530084960724453798370151865239021149462725 93
UVM_INFO @ 103215060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 111033213360353053462939070089903228016637124294398179963006357736868922327824 95
UVM_INFO @ 436002039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 38008597399013380240679167802955876514847856185747797754176320069424429829596 97
UVM_INFO @ 26183123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 29571422380799758040099099491481929948382984100880554123121967005661625674454 92
UVM_INFO @ 35244932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 51977327451954783501840584363065280650920618720259504628919069074593512425175 92
UVM_INFO @ 26815913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 91934766632236494084425261513944477618553417076686803974533588896264552193370 95
UVM_INFO @ 29711897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 40104952401775980700486122863752463159712962361228746716794679075164369554811 93
UVM_INFO @ 26608108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 1206781217212627049751537613600685740237610242059692039606293337180430421130 181
UVM_INFO @ 127296969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 47206535994571925247139322071399930794724520461743328745738725788299061789904 95
UVM_INFO @ 434604228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 104064207881154881201256257160624993948111855375893297117111610737945081910753 92
UVM_INFO @ 53645511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 46531176524675212692644013977083506071650811009360457466754580756853973647125 95
UVM_INFO @ 56528765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 37164855316991322624618777952222874418656407013744281515662184424686205051355 97
UVM_INFO @ 105774131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 34149244068028895478843669864397608805600768799877670949902697032307384696819 148
UVM_INFO @ 949322666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 85127715506809204383040089291421134209670488467166666660521021718798173844508 99
UVM_INFO @ 29807118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 98983727556071838427237307844552376270703993528353476732134814249856319080309 99
UVM_INFO @ 108874600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 10466593158144541401787078124749165178602358246009824677798882616651066020756 100
UVM_INFO @ 106858115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 57586590754459980735963197533442713286005691328756226249228977625021669549930 93
UVM_INFO @ 429902478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 53728330443731577909890546816249457804777393406658614577356832491384227276312 95
UVM_INFO @ 53368064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 86003244060055230123232625693430184333115464126799571088735712861860679918519 92
UVM_INFO @ 63667104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 40733948303319037901342449394885623518679465107913010645364539974186801647160 101
UVM_INFO @ 118342524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 4322362116710836190697042342905583643692083707212265245111079124011584356137 92
UVM_INFO @ 54248689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 81520777726570772588324098211691380653552779653979022469092298427516351919393 95
UVM_INFO @ 433360114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 3751851893470199260320542991395173556683834668625895601087643897837528706535 101
UVM_INFO @ 445376726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 106477766846626080620702564635551875775003612845702514412239608876854747818462 97
UVM_INFO @ 104829367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 76754022240105227727988798818820428378216029608670561646617567949623826591510 95
UVM_INFO @ 61321175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 71051389573113844488182830492103863879162620779263335748871781910356897334045 2123
UVM_INFO @ 354809144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 99796053600594472238235813831223954198514579166935253359387707693818845315951 97
UVM_INFO @ 52697494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 72590955451419941114869440027695195111041455628760935297542163355418451488385 93
UVM_INFO @ 56783339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 10089239798345467722993446141721153104521989790195481395367547715202321579273 330
UVM_INFO @ 71756805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 9782784310596207346806605247944767558537710599458766762560949619963963318785 103
UVM_INFO @ 99775314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 96535053470043649791908131884472470101563259023794965543941736100404077203661 95
UVM_INFO @ 53507539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 70221037537073836007024262771769427987345611451950315710698426539265127455827 92
UVM_INFO @ 424775952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 19203615509226737752532852048703655226684636691803310893139775167352768816432 92
UVM_INFO @ 52649198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 22407445934752454017222325939162981265360708881307577498584613072073680596051 92
UVM_INFO @ 106344089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 14457448878298774738442045953100557029658618494654673909710049484707813962975 101
UVM_INFO @ 105650420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 85376685980645054141680212978483132587721504879684484649811287009693654738163 97
UVM_INFO @ 432307962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 27469477349559584778750247140322991085691832556073931245093351455599871044163 92
UVM_INFO @ 431731830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 114004881119890828400006012943023250479171924977846645327042758794232938906381 97
UVM_INFO @ 53988140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 45521891048404507942228168787149203726132048054622370010633590000458851007748 152
UVM_INFO @ 75376286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 37413374971773983737648869542336467968694372314898793739524627030821588649308 97
UVM_INFO @ 27050027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 57809320341736655732665732964089217652342499818143525265032094278362545678731 93
UVM_INFO @ 52044705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 82275222426796056173292926222635235593928977011562775031799014994040533616938 95
UVM_INFO @ 42016267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 106793190045262625935563346067596635615159414373937162770861863654879048971077 99
UVM_INFO @ 55992986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1315) [otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_check_error does not trigger!
otp_ctrl_stress_all 110713180412236984690502880700303918747634723320280697634200957999532663038679 23955
UVM_INFO @ 72031100654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_background_chks 109374445215442637889954162745539555866918778935765192412763717503651330864332 22556
UVM_INFO @ 14962343254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 55736514872151103535944106347164708411100514930177114807278640314570371175962 9863
UVM_INFO @ 8315042156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_background_chks 8392013365114637417178382998682346232813986677710790869455260678840657281494 3251
UVM_INFO @ 6639796466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 23431506835037112385708116349970883535211509629715317359171462557599032031445 202701
UVM_INFO @ 124209681333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_background_chks 88319824037738542969459336667117460004780472750864078588582236377600407442365 1864
UVM_INFO @ 1233025665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 37974984578712615651443210501722116238928360812274536722043791523140552039906 57007
UVM_INFO @ 20288395486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 32074613943434357892717205882096702577768621458842270022015633927203840555092 20263
UVM_INFO @ 15700238963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 52115644827189926999082890484246888127205467485318226433039207132927654420002 12498
UVM_INFO @ 15363416157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 17330990128265091246018877224920600616375342444284126843542433967024901641628 55679
UVM_INFO @ 11658475857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 65953044441327868833674185051127766952019367654373226468840843109779324290368 50062
UVM_INFO @ 15681797190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 70800538866768240969326660237272875513770072951327737211887567468448068285654 3816
UVM_INFO @ 8092815259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 87571685390299520634756829803515585543598509050064757048776210308280052790735 52188
UVM_INFO @ 5040240561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 97440308785513190479864111310541463391389641887455308072983055208711481550027 38452
UVM_INFO @ 36135293329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [otp_ctrl_common_vseq] expect alert:fatal_check_error to fire
otp_ctrl_sec_cm 108031658926908051397831165114024311299827164673754799535326948104263389710841 1521
UVM_INFO @ 22870276893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_sec_cm 35301252641512722959041947319806876258763905587091339345203972094589754208431 2127
UVM_INFO @ 28261762241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:691) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: OtpErr
otp_ctrl_check_fail 24236606502232921509989606200340040633339711136802726134857054553583272378025 311
UVM_INFO @ 829752008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 37177214218058474792601925102016145253185223437679493234483654683104823863981 4360
UVM_INFO @ 2140747853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 50606631372212921203808187924007013276439794234739334756411038311218662887645 6240
UVM_INFO @ 310134376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert fatal_macro_error did not trigger max_delay:*
otp_ctrl_macro_errs 52434615897827116725133168282871111759355824985030690956890268651548885077979 347
UVM_INFO @ 222442776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 43798088243605910458702442561544950819833068971767721079518754183737082237828 507
UVM_INFO @ 160158663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 83056947283450097199472791388635892032961237894490062030900264418845103145962 4007
UVM_INFO @ 5017185229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:958) [scoreboard] Check failed (csr.get_mirrored_value() | status_mask) == (item.d_data | status_mask) (* [*] vs * [*]) reg name: status, compare_mask *
otp_ctrl_check_fail 40005596844729141261779491032431573314657476833768302533588577789601233652013 12595
UVM_INFO @ 13648795214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1315) [otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_check_error does not trigger!
otp_ctrl_init_fail 58069015530842009109929619831169690949260399888051330048226471360580612144204 1969
UVM_INFO @ 1701574501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 94851779184684038822775179167604689237697275709322228124218621891189373302745 1149
UVM_INFO @ 388343024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 110248366804115608721119878130036416746179690496087481964941588341789004552680 1747
UVM_INFO @ 1956247556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 95910313868181987706653678648146375502152186223058541833068951690424246815698 2023
UVM_INFO @ 1813054434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 27691435673920577321125536478332610991936951305120140772923777341437059279814 1007
UVM_INFO @ 246447088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 95832313856994276229027395519239922053074228541849428644974077778889615052073 2097
UVM_INFO @ 490356823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 732008168917635790449809937134725707085671655069013014737770269943229697024 1453
UVM_INFO @ 520779474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 72128386983963366561418830468449038447891382949812902010930350151330053951378 2089
UVM_INFO @ 1216228837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 57682398667844504445415099357108664342738479517732692610973351465376593239669 1343
UVM_INFO @ 210752529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 86792284593289351375215624501932446656715604427349690177804522918858815633837 1719
UVM_INFO @ 2431666816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 23322280929332114213218123026993350552023158256340789322966760077874639378356 1397
UVM_INFO @ 1341459827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 81429576723761807860137917649823137184310411741209174347101517282893030791301 1451
UVM_INFO @ 1586264746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 12915545450560672071783882639889059035717323456111870177329154252284204703653 1553
UVM_INFO @ 1745096150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 92267241708780245347553148810052410726662788277507714757501185972106679199912 1575
UVM_INFO @ 135692665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 110117770263749027957951715816757776295163086952231989068495565528228463623217 1443
UVM_INFO @ 362260234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state
otp_ctrl_check_fail 2883305636984669020612371504511308317684097225819043846049266949211955007589 2642
UVM_INFO @ 3202862767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---