| V1 |
|
100.00% |
| V2 |
|
84.05% |
| V2S |
|
100.00% |
| V3 |
|
6.00% |
| unmapped |
|
74.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 50 | 50 | 100.00 | |||
| pattgen_smoke | 3.000s | 46.036us | 50 | 50 | 100.00 | |
| csr_hw_reset | 5 | 5 | 100.00 | |||
| pattgen_csr_hw_reset | 2.000s | 17.471us | 5 | 5 | 100.00 | |
| csr_rw | 20 | 20 | 100.00 | |||
| pattgen_csr_rw | 2.000s | 52.633us | 20 | 20 | 100.00 | |
| csr_bit_bash | 5 | 5 | 100.00 | |||
| pattgen_csr_bit_bash | 3.000s | 188.184us | 5 | 5 | 100.00 | |
| csr_aliasing | 5 | 5 | 100.00 | |||
| pattgen_csr_aliasing | 1.000s | 51.313us | 5 | 5 | 100.00 | |
| csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 | |||
| pattgen_csr_mem_rw_with_rand_reset | 2.000s | 323.360us | 20 | 20 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 25 | 25 | 100.00 | |||
| pattgen_csr_rw | 2.000s | 52.633us | 20 | 20 | 100.00 | |
| pattgen_csr_aliasing | 1.000s | 51.313us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| perf | 24 | 50 | 48.00 | |||
| pattgen_perf | 3575.000s | 600000.000us | 24 | 50 | 48.00 | |
| cnt_rollover | 50 | 50 | 100.00 | |||
| cnt_rollover | 70.000s | 5263.885us | 50 | 50 | 100.00 | |
| error | 50 | 50 | 100.00 | |||
| pattgen_error | 2.000s | 39.097us | 50 | 50 | 100.00 | |
| stress_all | 17 | 50 | 34.00 | |||
| pattgen_stress_all | 10140.000s | 2747186.273us | 17 | 50 | 34.00 | |
| alert_test | 50 | 50 | 100.00 | |||
| pattgen_alert_test | 2.000s | 10.125us | 50 | 50 | 100.00 | |
| intr_test | 50 | 50 | 100.00 | |||
| pattgen_intr_test | 2.000s | 13.244us | 50 | 50 | 100.00 | |
| tl_d_oob_addr_access | 20 | 20 | 100.00 | |||
| pattgen_tl_errors | 3.000s | 159.315us | 20 | 20 | 100.00 | |
| tl_d_illegal_access | 20 | 20 | 100.00 | |||
| pattgen_tl_errors | 3.000s | 159.315us | 20 | 20 | 100.00 | |
| tl_d_outstanding_access | 50 | 50 | 100.00 | |||
| pattgen_csr_hw_reset | 2.000s | 17.471us | 5 | 5 | 100.00 | |
| pattgen_csr_rw | 2.000s | 52.633us | 20 | 20 | 100.00 | |
| pattgen_csr_aliasing | 1.000s | 51.313us | 5 | 5 | 100.00 | |
| pattgen_same_csr_outstanding | 2.000s | 43.300us | 20 | 20 | 100.00 | |
| tl_d_partial_access | 50 | 50 | 100.00 | |||
| pattgen_csr_hw_reset | 2.000s | 17.471us | 5 | 5 | 100.00 | |
| pattgen_csr_rw | 2.000s | 52.633us | 20 | 20 | 100.00 | |
| pattgen_csr_aliasing | 1.000s | 51.313us | 5 | 5 | 100.00 | |
| pattgen_same_csr_outstanding | 2.000s | 43.300us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 25 | 25 | 100.00 | |||
| pattgen_tl_intg_err | 2.000s | 181.579us | 20 | 20 | 100.00 | |
| pattgen_sec_cm | 2.000s | 70.259us | 5 | 5 | 100.00 | |
| sec_cm_bus_integrity | 20 | 20 | 100.00 | |||
| pattgen_tl_intg_err | 2.000s | 181.579us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 3 | 50 | 6.00 | |||
| pattgen_stress_all_with_rand_reset | 140.000s | 5076.236us | 3 | 50 | 6.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 37 | 50 | 74.00 | |||
| pattgen_inactive_level | 221.000s | 10031.387us | 37 | 50 | 74.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue | ||||
| pattgen_perf | 78316658154544889811129951144967607813206644020577029031459467199038561803488 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 41511142831796641579038185337361261122459458818760615600665280126760098787158 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 67091401697866904763420140660127268103975602824198489759644241567848969181370 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 44052904935159131131935109894868450304579929356148765251105652987842223236698 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 51299472016715378074009500500276072217466736566424554523665238590254412285558 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 9892340481042153114391069494888310364650859915743319545150179111823150951477 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 53204496921815077910295856453434060870022438101611053615872377638033193616941 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 53537718902317000622681252999665882283365526316944987054832856757104125561290 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 114816765975032345375202889139767089211487995855120000310108324032878770771572 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 114577599155632456753209411514985254417449229161988170454472206407432325994633 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 25236228825504215172245189978433889950856916472390924095548832904093008042304 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 78762165129704557851054476027450279121600910240527576909380446023410474976280 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 23377187932464899147723432423938386551407197889393823987463225976065056163039 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 33627028230192024793133136989202831711050353548101714082372796996025991326433 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 39134417266420961052806703812911603230659325781577720475482806832979389751874 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 77509658554426164893709920805217618003472479561223367605506938611042389248100 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 2864909574128514582145403427813582642816507097051330507850888259547374238898 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:1237) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | ||||
| pattgen_stress_all_with_rand_reset | 51865760014681977488638104751448940322031027577006480944499836212432570848640 | 130 |
UVM_ERROR @ 2172436285 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2172436285 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 2172610197 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 39394886061239867461543821736114688942909826327482498275286166311717456925807 | 267 |
UVM_ERROR @ 3444117076 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 3444117076 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 5/10
UVM_INFO @ 3444283740 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 93614920511445364587255444779715146504491610474620766205443064154142971505348 | 147 |
UVM_ERROR @ 382652987 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 382652987 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 382772987 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 76197211641326487974784130083088334749453887466411356360872104298464577341376 | 159 |
UVM_ERROR @ 7898330217 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 7898330217 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 7898538552 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 98710249705711305276945868482333371000670862355567607032274418575940557808229 | 159 |
UVM_ERROR @ 1620005320 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1620005320 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 1620069151 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 74044832213487654384651917484484262097964586037529719065681847529721614660362 | 137 |
UVM_ERROR @ 422236980 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 422236980 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 422277384 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 98148885625099801605722722399675983712587418624646518705611266497521366914972 | 114 |
UVM_ERROR @ 463701324 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 463701324 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 463864588 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 4415321442371761572831079029084764901940366880871934022530926431908672270128 | 196 |
UVM_ERROR @ 418685874 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 418685874 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 4/10
UVM_INFO @ 418828730 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 16609713161982456658822440824029048865723155999504142996174316961665664324538 | 117 |
UVM_ERROR @ 2037313397 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2037313397 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 2037661221 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 21836144526817498202784971535176455614957317809346293265413174780677333692647 | 168 |
UVM_ERROR @ 509477869 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 509477869 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 509518273 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 19139055649062438774768315176830049603816264710425533880888602738172504961211 | 118 |
UVM_ERROR @ 3822405769 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 3822405769 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 3822614104 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 60238771395205703561656527145409286484155604772693219833901831536397463575543 | 147 |
UVM_ERROR @ 858572516 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 858572516 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 858633740 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 58987142045997438562768849785935136507231815182037824765821056427278977804466 | 224 |
UVM_ERROR @ 946333543 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 946333543 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 4/10
UVM_INFO @ 946405706 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 90880180016368816377914953244531166338789731576076834919678313442743415325282 | 190 |
UVM_ERROR @ 2888180413 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2888180413 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 2888280413 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 54433026913967288130618051395473678713295950384444915321479411544335199217684 | 167 |
UVM_ERROR @ 2556285357 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2556285357 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 2556525357 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 57910458508314080978585822890260845685189669318709267508125236835455122573268 | 113 |
UVM_ERROR @ 108147731 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 108147731 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 108227731 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 99744643260527622153759078056784512476773768811369552280944554778155827870200 | 229 |
UVM_ERROR @ 16256888985 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 16256888985 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 3/10
UVM_INFO @ 16257707166 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 74154297608375856086331869793142183893922704701721478219515384854483330562869 | 125 |
UVM_ERROR @ 896792229 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 896792229 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 896979726 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 62819050585194341147683568543890759530575102246885932721642762832869629887329 | 117 |
UVM_ERROR @ 648332321 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 648332321 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 648366803 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 7774246531518643375237430707847030533924238952360675308919018767581021750169 | 157 |
UVM_ERROR @ 1785662609 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1785662609 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 1786037612 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 88448189689804481122957405772413654484988022088505824989456770672506018855381 | 124 |
UVM_ERROR @ 250128114 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 250128114 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 250148522 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 19647977877925178238684859597692136118489279899501569835556948919506134616335 | 115 |
UVM_ERROR @ 1013904767 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1013904767 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 1013944767 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 84183527705614895575344553647725078403318932355283425279666319805526242488522 | 216 |
UVM_ERROR @ 2814350357 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2814350357 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 3/5
UVM_INFO @ 2814493213 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 38327283758149380118586546140589234917465683878832553510218895710140456048845 | 121 |
UVM_ERROR @ 745079501 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 745079501 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 745227038 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 102682113881568094339130465558896289000929877107446627708975308454122127015005 | 394 |
UVM_ERROR @ 9015618014 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 9015618014 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 9/10
UVM_INFO @ 9015836764 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 81385333783708160331806782530551567719374348121612684041661533305633542553476 | 116 |
UVM_ERROR @ 1860080299 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1860080299 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 1860163633 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 73713656972560793492776717396058373583391542303430400348042096674967235839597 | 247 |
UVM_ERROR @ 2231917017 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2231917017 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 4/5
UVM_INFO @ 2231937219 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 73792154739176808482402817376470612879924361203605750324663367251362346837628 | 176 |
UVM_ERROR @ 21755520252 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 21755520252 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 3/10
UVM_INFO @ 21756120252 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 71701226108445852442437972005917673695156723248490244912157831582574927028498 | 157 |
UVM_ERROR @ 1389826595 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1389826595 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 1389866595 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 108590973888453967783250508183612528142359669548809739984206152666245390757540 | 113 |
UVM_ERROR @ 320073548 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 320073548 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 320220608 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 16897435088061270066131024879115105603844828229266930832198728815333619080858 | 185 |
UVM_ERROR @ 956543763 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 956543763 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 4/10
UVM_INFO @ 956823763 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 62015978269816543474226656263640386553734375780313799069072520635751045890722 | 122 |
UVM_ERROR @ 893564658 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 893564658 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 893635365 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 40071625138014405500683593051336758107246352658004140927761147424254773561311 | 132 |
UVM_ERROR @ 1038448861 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1038448861 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 1038553031 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 88345835005223598583774817835205501845046801865644446744780090956191253981094 | 277 |
UVM_ERROR @ 2042487696 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2042487696 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 4/10
UVM_INFO @ 2042519610 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 111588196906409737141080756288293352889951714518351612014200888460496304636916 | 113 |
UVM_ERROR @ 212649104 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 212649104 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 212832776 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 15352547899148534821704802947159392464698717565752122923870050905750351744251 | 115 |
UVM_ERROR @ 827604728 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 827604728 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 827717936 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 16667574447631045190613031169551344206233359345132618639505729913911773363148 | 185 |
UVM_ERROR @ 1047904723 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1047904723 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 3/10
UVM_INFO @ 1048275093 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 62490782233479157720215006232895662757040675095221897719130291310340342069380 | 162 |
UVM_ERROR @ 4078910204 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 4078910204 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 4079310204 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 28230261213841810990778378445726042087459978451215246921322648003391101882033 | 114 |
UVM_ERROR @ 300938418 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 300938418 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 300959694 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 106208534605331196781313418195126003274215684509865875218127165869779932864754 | 207 |
UVM_ERROR @ 1456943977 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1456943977 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 4/10
UVM_INFO @ 1457003977 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 19633078356802979939459633568005608123768942527464911447986195970897914023402 | 244 |
UVM_ERROR @ 1919456048 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1919456048 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 5/10
UVM_INFO @ 1919661176 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 75930649668138728129209752499168480343082763098972595467576286129484598714628 | 177 |
UVM_ERROR @ 4321406427 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 4321406427 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 4321726427 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 30727501505639459686567162129452104208318061952089574644503459298423872646645 | 119 |
UVM_ERROR @ 1602565230 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1602565230 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 1602646862 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 111566471200880857653004209184056429252357965547464122700311943400101760899022 | 121 |
UVM_ERROR @ 441677142 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 441677142 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 441727647 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 11577958451023867828237523255345523186825986579323534009027631778006761451926 | 175 |
UVM_ERROR @ 1524861410 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1524861410 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 1524954191 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 43240204416697816069008307070603866165289434516288319759640459363716268336700 | 261 |
UVM_ERROR @ 21160011935 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 21160011935 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 4/5
UVM_INFO @ 21160583363 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 5349397270852347445204253885631982887769900314892892519810514725974093366557 | 150 |
UVM_ERROR @ 314916272 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 314916272 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 314999608 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| Job killed! | ||||
| pattgen_stress_all | 19207289335359937522816723338519258494141081368704885379470551199955762597964 | None | ||
| pattgen_stress_all | 28165890869761527795890364576885348505643252741174287268667241863450959026674 | None | ||
| pattgen_perf | 71334688016445092351291716645189235355314568814466350152674191265457196320508 | None | ||
| pattgen_perf | 86837485184976124856220747405197092003238251109066798715922585944570596727949 | None | ||
| pattgen_stress_all | 36397786161873495405610207087539801010837295995868832080504092681063323641989 | None | ||
| pattgen_perf | 25527251302067219038108375569887153275058070403394259993281164941756718187652 | None | ||
| pattgen_perf | 12998870283866799742751217494691283650590550316145094696098089581538886129259 | None | ||
| pattgen_stress_all | 111635248594313970273722268561994253406056068817199901077857725131114685932919 | None | ||
| pattgen_perf | 50125304507095022098711229830788320468855016341347032221965858845685595746653 | None | ||
| pattgen_stress_all | 63167356120402313625341897426298613776560927850644028208649268701081398032426 | None | ||
| pattgen_perf | 47433059720855832468652108051300621543844017675895327525246578286569820764886 | None | ||
| pattgen_stress_all | 74586759601462690959389109910426138843049810416621782942965879027107099268560 | None | ||
| pattgen_perf | 114181340442248715022270703684931125002451366479791677294353994028554163721559 | None | ||
| pattgen_stress_all | 95433964369494397440105895312043535002720718084604342794151341517999998166549 | None | ||
| pattgen_perf | 9121324832285991253228566544263803118742147672717645578224334070085221679002 | None | ||
| pattgen_stress_all | 77820985729816391266757885791835199286717282239333561470610827140034188418149 | None | ||
| pattgen_perf | 95754875556625528012525204933796892921522018010686714014612550834466226583266 | None | ||
| pattgen_stress_all | 99842327993387958833990847498749969324358201140774836164830528722242738214295 | None | ||
| pattgen_stress_all | 2907935795842708783503824172124958954559262832613170356025797436588936490944 | None | ||
| pattgen_stress_all | 79619726594665473895817566685218056623118492678252863590661609413638122561262 | None | ||
| pattgen_stress_all | 51198889905606834401642459157710814944238438012347016528106563475808278863916 | None | ||
| pattgen_stress_all | 74470895818134943171617249514840301876539472526726398347259606821109249704566 | None | ||
| pattgen_stress_all | 92929168322656771596793528624934847174130965968022633403828389448574694673283 | None | ||
| UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: | ||||
| pattgen_stress_all | 70132482208462058920341669045603854741119844593483753531686740230665371393181 | 130 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10189
|
|
| pattgen_stress_all | 33502797054693729567944591709455816097705554213940698987778424913230237210385 | 125 |
--------------------------------------
Name Type Size Value
--------------------------------------
exp_item pattgen_item - @12125
|
|
| pattgen_stress_all | 19286396443769918254356928194667015496843957396255180772333359836213685248673 | 130 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10193
|
|
| pattgen_stress_all | 43607090737940491295546160266138027296538918794007329094491609795200785754376 | 138 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10182
|
|
| pattgen_stress_all | 41019823380807681018607699323772674676478741422608369302746542409148848369900 | 137 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10205
|
|
| pattgen_stress_all | 81464152676754587595181104583776394933257923256314984969014553768690500466394 | 125 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10167
|
|
| pattgen_stress_all | 31287837838486728586291203932383322142905461256776939514262273836925617572947 | 133 |
----------------------------------------
Name Type Size Value
----------------------------------------
exp_item pattgen_item - @10111
|
|
| pattgen_stress_all | 49331617619522360968670732668184558361787748214915915243938056859164786253844 | 136 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10108
|
|
| pattgen_stress_all | 38961434398529744757957733302717898046935075076311420764823003787537336188346 | 145 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10254
|
|
| pattgen_stress_all | 2028740409355892583900177082097976135909570834377860191567933877424486452536 | 136 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10207
|
|
| pattgen_stress_all | 95766114659948159969065044508362180581779639139696890380424470185649378891955 | 138 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10082
|
|
| pattgen_stress_all | 81342199185667346347630475919907246979814580559516822214117053419401535662012 | 125 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10162
|
|
| pattgen_stress_all | 21124915474440124493991743344422239855719757301643528416884655210239530815067 | 155 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10307
|
|
| pattgen_stress_all | 113521915278146300179971969403847005789307198542521217111876143739912734282285 | 154 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10196
|
|
| pattgen_stress_all | 44392204949510104473644099207397620668967399026532398539638787227582947393337 | 151 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10253
|
|
| pattgen_stress_all | 72520927424447972593388686443576188280200804593386576497110201370861133522591 | 157 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11487
|
|
| pattgen_stress_all | 23132162847385662519535822688305868631370368404301666577946963624535809452432 | 142 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10327
|
|
| pattgen_stress_all | 51217336970104589555872139650434534264958855983215576606515713419277088582061 | 147 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10084
|
|
| pattgen_stress_all | 14677016546484892428868096853931296327011727289602337525718929808487708539167 | 148 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10708
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=21) | ||||
| pattgen_inactive_level | 6676788556339228927141051829126033869241562416068141505911551336180655338228 | 99 |
UVM_INFO @ 10031387455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) | ||||
| pattgen_inactive_level | 17512965899536514418856617626512434270199177190641434179172294141043690516705 | 99 |
UVM_INFO @ 10002386425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) | ||||
| pattgen_inactive_level | 79732882027922975954837885449010991206360993647603932929070087452170871302376 | 99 |
UVM_INFO @ 10045824248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_inactive_level | 56814007810805246603974420735689558225907137002003298703991225666972187935524 | 99 |
UVM_INFO @ 10025675406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) | ||||
| pattgen_inactive_level | 112155023555135217582449981247204121731382092689934961353830977779948906266579 | 99 |
UVM_INFO @ 10009614605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) | ||||
| pattgen_inactive_level | 88353607093290529800424703953261687508146695230875112579618455907547077223287 | 99 |
UVM_INFO @ 10007269407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) | ||||
| pattgen_inactive_level | 70026677559570657433363490096739076670152669041970621006709609478661263290620 | 99 |
UVM_INFO @ 10041072251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) | ||||
| pattgen_inactive_level | 41764557481441882245172553605640232375635004721283589978334757868566756874089 | 99 |
UVM_INFO @ 10009564680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_inactive_level | 46593331632254414114070114042925814481112855214367762774186435188824602795522 | 99 |
UVM_INFO @ 10012163512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=23) | ||||
| pattgen_inactive_level | 67299227430071513087343619385808897512528713083231689645061995829839097279901 | 99 |
UVM_INFO @ 10023863797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=18) | ||||
| pattgen_inactive_level | 17977565168316089740231867437275213650262652486858442779827464260852678189405 | 99 |
UVM_INFO @ 10037924464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) | ||||
| pattgen_inactive_level | 82892396098890116640193540839770473036089315646385532455921902881893872028928 | 99 |
UVM_INFO @ 10019334699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) | ||||
| pattgen_inactive_level | 24564356765737787232370741392549155197376697864879344533636635284781290010062 | 99 |
UVM_INFO @ 10015660937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|