| V1 |
|
98.75% |
| V2 |
|
98.75% |
| unmapped |
|
80.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| prim_alert_request_test | 79 | 80 | 98.75 | |||
| prim_async_alert | 0.700s | 11.400us | 20 | 20 | 100.00 | |
| prim_async_fatal_alert | 0.730s | 30.736us | 19 | 20 | 95.00 | |
| prim_sync_alert | 0.700s | 9.010us | 20 | 20 | 100.00 | |
| prim_sync_fatal_alert | 0.720s | 27.484us | 20 | 20 | 100.00 | |
| prim_alert_test | 79 | 80 | 98.75 | |||
| prim_async_alert | 0.700s | 11.400us | 20 | 20 | 100.00 | |
| prim_async_fatal_alert | 0.730s | 30.736us | 19 | 20 | 95.00 | |
| prim_sync_alert | 0.700s | 9.010us | 20 | 20 | 100.00 | |
| prim_sync_fatal_alert | 0.720s | 27.484us | 20 | 20 | 100.00 | |
| prim_alert_ping_request_test | 79 | 80 | 98.75 | |||
| prim_async_alert | 0.700s | 11.400us | 20 | 20 | 100.00 | |
| prim_async_fatal_alert | 0.730s | 30.736us | 19 | 20 | 95.00 | |
| prim_sync_alert | 0.700s | 9.010us | 20 | 20 | 100.00 | |
| prim_sync_fatal_alert | 0.720s | 27.484us | 20 | 20 | 100.00 | |
| prim_alert_integrity_errors_test | 79 | 80 | 98.75 | |||
| prim_async_alert | 0.700s | 11.400us | 20 | 20 | 100.00 | |
| prim_async_fatal_alert | 0.730s | 30.736us | 19 | 20 | 95.00 | |
| prim_sync_alert | 0.700s | 9.010us | 20 | 20 | 100.00 | |
| prim_sync_fatal_alert | 0.720s | 27.484us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| prim_alert_init_trigger_test | 79 | 80 | 98.75 | |||
| prim_async_alert | 0.700s | 11.400us | 20 | 20 | 100.00 | |
| prim_async_fatal_alert | 0.730s | 30.736us | 19 | 20 | 95.00 | |
| prim_sync_alert | 0.700s | 9.010us | 20 | 20 | 100.00 | |
| prim_sync_fatal_alert | 0.720s | 27.484us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 16 | 20 | 80.00 | |||
| prim_async_fatal_alert_with_3_cycles_skew | 0.720s | 30.228us | 16 | 20 | 80.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Offending 'ping_ok_o' | ||||
| prim_async_fatal_alert_with_3_cycles_skew | 48955977081554959144883558892550182219775576837603296013965780434135835493052 | 100 |
UVM_ERROR src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv(312) @ 31104000: reporter [ASSERT FAILED] PingResponse1_A
Starting assertion attempts at time 31123715ps: level = 0 arg = i_alert_receiver.PingDiffOk_A (from inst prim_alert_tb (src/lowrisc_dv_prim_alert_sim_0.1/tb/prim_alert_tb.sv:254))
[prim_alert_seq] Ping signal integrity error sequence finished!
|
|
| prim_async_fatal_alert | 32291439594346798583878290917372160272845555572071359569404749842323072668779 | 100 |
UVM_ERROR src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv(312) @ 30867000: reporter [ASSERT FAILED] PingResponse1_A
Starting assertion attempts at time 30896591ps: level = 0 arg = i_alert_receiver.PingDiffOk_A (from inst prim_alert_tb (src/lowrisc_dv_prim_alert_sim_0.1/tb/prim_alert_tb.sv:254))
[prim_alert_seq] Ping signal integrity error sequence finished!
|
|
| Offending 'alert_o' | ||||
| prim_async_fatal_alert_with_3_cycles_skew | 9074007074438099288318047497121449589812711527169298121748133764861540247822 | 100 |
UVM_ERROR src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv(320) @ 31140000: reporter [ASSERT FAILED] Alert_A
Starting assertion attempts at time 31199637ps: level = 0 arg = i_alert_receiver.PingDiffOk_A (from inst prim_alert_tb (src/lowrisc_dv_prim_alert_sim_0.1/tb/prim_alert_tb.sv:254))
[prim_alert_seq] Ping signal integrity error sequence finished!
|
|
| prim_async_fatal_alert_with_3_cycles_skew | 24181169222554633762891123368057579457966709699013694162623570728208587122350 | 100 |
UVM_ERROR src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv(320) @ 30519000: reporter [ASSERT FAILED] Alert_A
Starting assertion attempts at time 30578564ps: level = 0 arg = i_alert_receiver.PingDiffOk_A (from inst prim_alert_tb (src/lowrisc_dv_prim_alert_sim_0.1/tb/prim_alert_tb.sv:254))
[prim_alert_seq] Ping signal integrity error sequence finished!
|
|
| prim_async_fatal_alert_with_3_cycles_skew | 13619112576399055982214612452192408986437376849666463197542871470315920427191 | 100 |
UVM_ERROR src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv(320) @ 30818000: reporter [ASSERT FAILED] Alert_A
Starting assertion attempts at time 30888216ps: level = 0 arg = i_alert_receiver.PingDiffOk_A (from inst prim_alert_tb (src/lowrisc_dv_prim_alert_sim_0.1/tb/prim_alert_tb.sv:254))
[prim_alert_seq] Ping signal integrity error sequence finished!
|
|