Simulation Results: rom_ctrl/32kb

 
12/04/2026 00:11:27 DVSim: v1.29.0 sha: 4a305de json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.55 %
  • code
  • 99.58 %
  • assert
  • 96.80 %
  • func
  • 99.28 %
  • line
  • 99.59 %
  • branch
  • 99.64 %
  • cond
  • 98.66 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
98.55%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 4.450s 593.471us 2 2 100.00
csr_hw_reset 5 5 100.00
rom_ctrl_csr_hw_reset 8.540s 213.237us 5 5 100.00
csr_rw 20 20 100.00
rom_ctrl_csr_rw 9.050s 1045.254us 20 20 100.00
csr_bit_bash 5 5 100.00
rom_ctrl_csr_bit_bash 5.390s 296.083us 5 5 100.00
csr_aliasing 5 5 100.00
rom_ctrl_csr_aliasing 5.150s 1728.130us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.810s 194.148us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rom_ctrl_csr_rw 9.050s 1045.254us 20 20 100.00
rom_ctrl_csr_aliasing 5.150s 1728.130us 5 5 100.00
mem_walk 5 5 100.00
rom_ctrl_mem_walk 6.790s 3841.373us 5 5 100.00
mem_partial_access 5 5 100.00
rom_ctrl_mem_partial_access 5.270s 580.061us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 5.740s 178.432us 2 2 100.00
stress_all 20 20 100.00
rom_ctrl_stress_all 32.610s 4289.410us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 8.210s 741.409us 2 2 100.00
alert_test 50 50 100.00
rom_ctrl_alert_test 9.180s 775.871us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rom_ctrl_tl_errors 10.170s 170.545us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rom_ctrl_tl_errors 10.170s 170.545us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rom_ctrl_csr_hw_reset 8.540s 213.237us 5 5 100.00
rom_ctrl_csr_rw 9.050s 1045.254us 20 20 100.00
rom_ctrl_csr_aliasing 5.150s 1728.130us 5 5 100.00
rom_ctrl_same_csr_outstanding 8.930s 538.200us 20 20 100.00
tl_d_partial_access 50 50 100.00
rom_ctrl_csr_hw_reset 8.540s 213.237us 5 5 100.00
rom_ctrl_csr_rw 9.050s 1045.254us 20 20 100.00
rom_ctrl_csr_aliasing 5.150s 1728.130us 5 5 100.00
rom_ctrl_same_csr_outstanding 8.930s 538.200us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 19 20 95.00
rom_ctrl_corrupt_sig_fatal_chk 113.670s 10537.369us 19 20 95.00
passthru_mem_tl_intg_err 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 36.710s 3151.284us 20 20 100.00
tl_intg_err 25 25 100.00
rom_ctrl_sec_cm 291.440s 1679.959us 5 5 100.00
rom_ctrl_tl_intg_err 64.870s 533.262us 20 20 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 291.440s 1679.959us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 291.440s 1679.959us 5 5 100.00
sec_cm_checker_ctr_consistency 19 20 95.00
rom_ctrl_corrupt_sig_fatal_chk 113.670s 10537.369us 19 20 95.00
sec_cm_checker_ctrl_flow_consistency 19 20 95.00
rom_ctrl_corrupt_sig_fatal_chk 113.670s 10537.369us 19 20 95.00
sec_cm_checker_fsm_local_esc 19 20 95.00
rom_ctrl_corrupt_sig_fatal_chk 113.670s 10537.369us 19 20 95.00
sec_cm_compare_ctrl_flow_consistency 19 20 95.00
rom_ctrl_corrupt_sig_fatal_chk 113.670s 10537.369us 19 20 95.00
sec_cm_compare_ctr_consistency 19 20 95.00
rom_ctrl_corrupt_sig_fatal_chk 113.670s 10537.369us 19 20 95.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 291.440s 1679.959us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 291.440s 1679.959us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 4.450s 593.471us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 4.450s 593.471us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 4.450s 593.471us 2 2 100.00
sec_cm_bus_integrity 20 20 100.00
rom_ctrl_tl_intg_err 64.870s 533.262us 20 20 100.00
sec_cm_bus_local_esc 21 22 95.45
rom_ctrl_corrupt_sig_fatal_chk 113.670s 10537.369us 19 20 95.00
rom_ctrl_kmac_err_chk 8.210s 741.409us 2 2 100.00
sec_cm_mux_mubi 19 20 95.00
rom_ctrl_corrupt_sig_fatal_chk 113.670s 10537.369us 19 20 95.00
sec_cm_mux_consistency 19 20 95.00
rom_ctrl_corrupt_sig_fatal_chk 113.670s 10537.369us 19 20 95.00
sec_cm_ctrl_redun 19 20 95.00
rom_ctrl_corrupt_sig_fatal_chk 113.670s 10537.369us 19 20 95.00
sec_cm_ctrl_mem_integrity 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 36.710s 3151.284us 20 20 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 291.440s 1679.959us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 20 20 100.00
rom_ctrl_stress_all_with_rand_reset 530.740s 4834.945us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
rom_ctrl_corrupt_sig_fatal_chk 21492695695859470870628200122387725119880249128238727336883970401380181605289 88
UVM_INFO @ 3407310062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---