| V1 |
|
100.00% |
| V2 |
|
92.08% |
| V2S |
|
100.00% |
| V3 |
|
47.50% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random | 20 | 20 | 100.00 | |||
| rv_timer_random | 2.810s | 1315.090us | 20 | 20 | 100.00 | |
| csr_hw_reset | 5 | 5 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.940s | 18.137us | 5 | 5 | 100.00 | |
| csr_rw | 20 | 20 | 100.00 | |||
| rv_timer_csr_rw | 0.950s | 21.674us | 20 | 20 | 100.00 | |
| csr_bit_bash | 5 | 5 | 100.00 | |||
| rv_timer_csr_bit_bash | 3.900s | 558.366us | 5 | 5 | 100.00 | |
| csr_aliasing | 5 | 5 | 100.00 | |||
| rv_timer_csr_aliasing | 1.090s | 25.323us | 5 | 5 | 100.00 | |
| csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 | |||
| rv_timer_csr_mem_rw_with_rand_reset | 1.800s | 35.724us | 20 | 20 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 25 | 25 | 100.00 | |||
| rv_timer_csr_rw | 0.950s | 21.674us | 20 | 20 | 100.00 | |
| rv_timer_csr_aliasing | 1.090s | 25.323us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random_reset | 1 | 20 | 5.00 | |||
| rv_timer_random_reset | 2.970s | 163.471us | 1 | 20 | 5.00 | |
| disabled | 20 | 20 | 100.00 | |||
| rv_timer_disabled | 4.790s | 2057.740us | 20 | 20 | 100.00 | |
| cfg_update_on_fly | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 460.530s | 281142.999us | 10 | 10 | 100.00 | |
| no_interrupt_test | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 460.530s | 281142.999us | 10 | 10 | 100.00 | |
| stress | 20 | 20 | 100.00 | |||
| rv_timer_stress_all | 13.430s | 6235.701us | 20 | 20 | 100.00 | |
| alert_test | 50 | 50 | 100.00 | |||
| rv_timer_alert_test | 0.920s | 16.851us | 50 | 50 | 100.00 | |
| intr_test | 50 | 50 | 100.00 | |||
| rv_timer_intr_test | 0.930s | 15.142us | 50 | 50 | 100.00 | |
| tl_d_oob_addr_access | 20 | 20 | 100.00 | |||
| rv_timer_tl_errors | 3.690s | 307.092us | 20 | 20 | 100.00 | |
| tl_d_illegal_access | 20 | 20 | 100.00 | |||
| rv_timer_tl_errors | 3.690s | 307.092us | 20 | 20 | 100.00 | |
| tl_d_outstanding_access | 50 | 50 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.940s | 18.137us | 5 | 5 | 100.00 | |
| rv_timer_csr_rw | 0.950s | 21.674us | 20 | 20 | 100.00 | |
| rv_timer_csr_aliasing | 1.090s | 25.323us | 5 | 5 | 100.00 | |
| rv_timer_same_csr_outstanding | 1.210s | 38.706us | 20 | 20 | 100.00 | |
| tl_d_partial_access | 50 | 50 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.940s | 18.137us | 5 | 5 | 100.00 | |
| rv_timer_csr_rw | 0.950s | 21.674us | 20 | 20 | 100.00 | |
| rv_timer_csr_aliasing | 1.090s | 25.323us | 5 | 5 | 100.00 | |
| rv_timer_same_csr_outstanding | 1.210s | 38.706us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 25 | 25 | 100.00 | |||
| rv_timer_sec_cm | 1.430s | 607.279us | 5 | 5 | 100.00 | |
| rv_timer_tl_intg_err | 2.100s | 1219.209us | 20 | 20 | 100.00 | |
| sec_cm_bus_integrity | 20 | 20 | 100.00 | |||
| rv_timer_tl_intg_err | 2.100s | 1219.209us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| min_value | 2 | 10 | 20.00 | |||
| rv_timer_min | 4.340s | 1637.281us | 2 | 10 | 20.00 | |
| max_value | 0 | 10 | 0.00 | |||
| rv_timer_max | 2.070s | 88.904us | 0 | 10 | 0.00 | |
| stress_all_with_rand_reset | 17 | 20 | 85.00 | |||
| rv_timer_stress_all_with_rand_reset | 79.280s | 84365.499us | 17 | 20 | 85.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * | ||||
| rv_timer_min | 44593825702691733907892734867291198498989987321166676270887831816955879775475 | 76 |
UVM_INFO @ 70580836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 40749570299459739418642819998463676640868713875559032423700155305711151260351 | 75 |
UVM_INFO @ 606169713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 32339976148292756522236849413213199240861414314661270695551928319010920990022 | 76 |
UVM_INFO @ 122966253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 76703632749372208266891466741128449793971113953988479333611252472165102275322 | 75 |
UVM_INFO @ 98278012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 7965784517578425492788851274732318550393558162487184686751515095151583600346 | 76 |
UVM_INFO @ 71145344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 89373370074452033679436571641130025471818817939132279152524359121998085902386 | 75 |
UVM_INFO @ 63144299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 37904667305596271917157129817510589974293412739447339791099756478625266039551 | 75 |
UVM_INFO @ 354884013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 12408830651390882026924083330079048676494780413080135669225211640759258167273 | 75 |
UVM_INFO @ 298902548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 11527997210137748724463789343364797070713822649554179407649274159701762402873 | 75 |
UVM_INFO @ 125861183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 86476021143552369864292610194120501881734140640014682841667696916109886570844 | 75 |
UVM_INFO @ 468691083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 38596001837963595633485193329874354556730490243571331078758785903860451109242 | 75 |
UVM_INFO @ 433706758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 73221622945177561492888027263896113839371131101561992233759878376249128576392 | 76 |
UVM_INFO @ 1637281488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 12961710118741245248458176853222882687288814479927735251893490535372682468304 | 76 |
UVM_INFO @ 228692019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 105983525391324741464119047979897563434666458543538278302397583534098732106824 | 75 |
UVM_INFO @ 872431461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 106840092824005880128974276120012235077743557987495024503596749504988516351263 | 75 |
UVM_INFO @ 163471389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 67814421429229816255471488642126499932744130061986980788844802100187497118924 | 76 |
UVM_INFO @ 66905810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 77507457181028098444616283287162854079185834651852221993748646661606773025631 | 76 |
UVM_INFO @ 130824234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 114552814987347719314238734266662062685606806929323717128679227475183332975998 | 75 |
UVM_INFO @ 89084953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 4975036313004875418680098275523705753468778840344223799069673240636531705178 | 75 |
UVM_INFO @ 406574853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 1864727740969357556940559732138668358994921508031347098543535866108119275610 | 75 |
UVM_INFO @ 144351740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 25100485411061674918246890852522801614750536529250618752952897559220099362777 | 75 |
UVM_INFO @ 231372282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 88250185222512595001921943043917082751832164769200919431754706771857691146301 | 76 |
UVM_INFO @ 312596983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 78140195331192420087926159083617012198458705171614489261096211790531334422303 | 75 |
UVM_INFO @ 1056804247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 35626102848621724324856336255451429890080294816132140481485255625336595093138 | 75 |
UVM_INFO @ 94891304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 85272354213606498658210222063839238451163471048382537614279284666603078162997 | 75 |
UVM_INFO @ 963916917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 103258943494651188563224688683040646694214049556355425192678220925186390945606 | 76 |
UVM_INFO @ 169213828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 46703325154350022760932890198989052347491740359087425901400777863001239021916 | 75 |
UVM_INFO @ 160952314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) | ||||
| rv_timer_max | 29274928800326293116334891431470542957161883652465368638821881752915768978489 | 75 |
UVM_INFO @ 58111035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 110140642373758061043445351605211072854667629353597706265051155251759374629493 | 75 |
UVM_INFO @ 44132215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 68879249862597743836658911505807363552094755236047729338937218650710413530160 | 75 |
UVM_INFO @ 527134843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 63568777319839611313547751913865820720560435902803694719770949508270705335891 | 75 |
UVM_INFO @ 92850274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 33642295104850292500220830249400257442240124467774436378829701007440947527516 | 75 |
UVM_INFO @ 239536539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 115222896741092056824093831732028728355217287598035293395942499710230336668861 | 76 |
UVM_INFO @ 176948299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 64556423936134084264442871405362058581887952677097335409862230828890641347530 | 75 |
UVM_INFO @ 88580440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 103786171583374256178433953024175731859357290121320230076999619014022404262343 | 75 |
UVM_INFO @ 90507629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (rv_timer_scoreboard.sv:346) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*]) | ||||
| rv_timer_max | 81373483402680269285250976030349669747983175352349805136517917521076246311684 | 75 |
UVM_INFO @ 81248863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 93425072524912435385826043446344364325392013635704142272138553209049049487896 | 75 |
UVM_INFO @ 88904209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (cip_base_vseq.sv:1170) [rv_timer_common_vseq] Check failed (vseq_done) | ||||
| rv_timer_stress_all_with_rand_reset | 97384321873208254240282858577848075187161939431438451625750442695706667303197 | 162 |
UVM_INFO @ 1893075365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 113278441858790573373789440138497075860706546916607784041797995457476603510252 | 104 |
UVM_INFO @ 3217035489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues | ||||
| rv_timer_stress_all_with_rand_reset | 72893542973218563146816094133719555438339809791880226927824807865808947961923 | 186 |
UVM_INFO @ 1323858640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|