Simulation Results: spi_device/2p

 
12/04/2026 00:11:27 DVSim: v1.29.0 sha: 4a305de json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.06 %
  • code
  • 94.28 %
  • assert
  • 94.74 %
  • func
  • 99.16 %
  • line
  • 99.16 %
  • branch
  • 98.49 %
  • cond
  • 96.65 %
  • toggle
  • 87.74 %
  • FSM
  • 89.36 %
Validation stages
V1
99.13%
V2
99.81%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 49 50 98.00
spi_device_flash_and_tpm 379.960s 54501.600us 49 50 98.00
csr_hw_reset 5 5 100.00
spi_device_csr_hw_reset 1.850s 41.535us 5 5 100.00
csr_rw 20 20 100.00
spi_device_csr_rw 3.330s 250.592us 20 20 100.00
csr_bit_bash 5 5 100.00
spi_device_csr_bit_bash 29.680s 861.720us 5 5 100.00
csr_aliasing 5 5 100.00
spi_device_csr_aliasing 19.190s 1242.981us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
spi_device_csr_mem_rw_with_rand_reset 4.350s 223.227us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
spi_device_csr_rw 3.330s 250.592us 20 20 100.00
spi_device_csr_aliasing 19.190s 1242.981us 5 5 100.00
mem_walk 5 5 100.00
spi_device_mem_walk 1.080s 14.062us 5 5 100.00
mem_partial_access 5 5 100.00
spi_device_mem_partial_access 2.730s 59.813us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 50 50 100.00
spi_device_csb_read 1.190s 14.357us 50 50 100.00
mem_parity 20 20 100.00
spi_device_mem_parity 1.530s 66.451us 20 20 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 1.110s 60.675us 1 1 100.00
tpm_read 50 50 100.00
spi_device_tpm_rw 8.110s 319.800us 50 50 100.00
tpm_write 50 50 100.00
spi_device_tpm_rw 8.110s 319.800us 50 50 100.00
tpm_hw_reg 100 100 100.00
spi_device_tpm_read_hw_reg 19.680s 6564.429us 50 50 100.00
spi_device_tpm_sts_read 1.380s 549.851us 50 50 100.00
tpm_fully_random_case 50 50 100.00
spi_device_tpm_all 39.770s 22865.061us 50 50 100.00
pass_cmd_filtering 100 100 100.00
spi_device_pass_cmd_filtering 39.000s 200749.086us 50 50 100.00
spi_device_flash_all 430.260s 84819.338us 50 50 100.00
pass_addr_translation 100 100 100.00
spi_device_pass_addr_payload_swap 38.670s 73306.064us 50 50 100.00
spi_device_flash_all 430.260s 84819.338us 50 50 100.00
pass_payload_translation 100 100 100.00
spi_device_pass_addr_payload_swap 38.670s 73306.064us 50 50 100.00
spi_device_flash_all 430.260s 84819.338us 50 50 100.00
cmd_info_slots 50 50 100.00
spi_device_flash_all 430.260s 84819.338us 50 50 100.00
cmd_read_status 100 100 100.00
spi_device_intercept 20.200s 2828.252us 50 50 100.00
spi_device_flash_all 430.260s 84819.338us 50 50 100.00
cmd_read_jedec 100 100 100.00
spi_device_intercept 20.200s 2828.252us 50 50 100.00
spi_device_flash_all 430.260s 84819.338us 50 50 100.00
cmd_read_sfdp 100 100 100.00
spi_device_intercept 20.200s 2828.252us 50 50 100.00
spi_device_flash_all 430.260s 84819.338us 50 50 100.00
cmd_fast_read 100 100 100.00
spi_device_intercept 20.200s 2828.252us 50 50 100.00
spi_device_flash_all 430.260s 84819.338us 50 50 100.00
cmd_read_pipeline 100 100 100.00
spi_device_intercept 20.200s 2828.252us 50 50 100.00
spi_device_flash_all 430.260s 84819.338us 50 50 100.00
flash_cmd_upload 49 50 98.00
spi_device_upload 1940.730s 1500000.000us 49 50 98.00
mailbox_command 50 50 100.00
spi_device_mailbox 70.120s 12041.205us 50 50 100.00
mailbox_cross_outside_command 50 50 100.00
spi_device_mailbox 70.120s 12041.205us 50 50 100.00
mailbox_cross_inside_command 50 50 100.00
spi_device_mailbox 70.120s 12041.205us 50 50 100.00
cmd_read_buffer 100 100 100.00
spi_device_flash_mode 36.750s 21973.208us 50 50 100.00
spi_device_read_buffer_direct 17.260s 6625.830us 50 50 100.00
cmd_dummy_cycle 100 100 100.00
spi_device_mailbox 70.120s 12041.205us 50 50 100.00
spi_device_flash_all 430.260s 84819.338us 50 50 100.00
quad_spi 50 50 100.00
spi_device_flash_all 430.260s 84819.338us 50 50 100.00
dual_spi 50 50 100.00
spi_device_flash_all 430.260s 84819.338us 50 50 100.00
4b_3b_feature 50 50 100.00
spi_device_cfg_cmd 21.900s 3764.049us 50 50 100.00
write_enable_disable 50 50 100.00
spi_device_cfg_cmd 21.900s 3764.049us 50 50 100.00
TPM_with_flash_or_passthrough_mode 49 50 98.00
spi_device_flash_and_tpm 379.960s 54501.600us 49 50 98.00
tpm_and_flash_trans_with_min_inactive_time 50 50 100.00
spi_device_flash_and_tpm_min_idle 494.410s 394549.526us 50 50 100.00
stress_all 50 50 100.00
spi_device_stress_all 963.920s 465925.651us 50 50 100.00
alert_test 50 50 100.00
spi_device_alert_test 1.130s 35.121us 50 50 100.00
intr_test 50 50 100.00
spi_device_intr_test 1.150s 55.196us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
spi_device_tl_errors 6.230s 411.587us 20 20 100.00
tl_d_illegal_access 20 20 100.00
spi_device_tl_errors 6.230s 411.587us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
spi_device_csr_hw_reset 1.850s 41.535us 5 5 100.00
spi_device_csr_rw 3.330s 250.592us 20 20 100.00
spi_device_csr_aliasing 19.190s 1242.981us 5 5 100.00
spi_device_same_csr_outstanding 5.120s 156.090us 20 20 100.00
tl_d_partial_access 50 50 100.00
spi_device_csr_hw_reset 1.850s 41.535us 5 5 100.00
spi_device_csr_rw 3.330s 250.592us 20 20 100.00
spi_device_csr_aliasing 19.190s 1242.981us 5 5 100.00
spi_device_same_csr_outstanding 5.120s 156.090us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
spi_device_sec_cm 1.760s 101.393us 5 5 100.00
spi_device_tl_intg_err 20.120s 3268.223us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
spi_device_tl_intg_err 20.120s 3268.223us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 50 50 100.00
spi_device_flash_mode_ignore_cmds 367.760s 330587.361us 50 50 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
spi_device_upload 8360725015098787392680957264456571023624611728044832107575622186653995276778 87
UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (spi_device_scoreboard.sv:2512) [scoreboard] Check failed item.d_data == `gmv(csr) (* [*] vs * [*]) CSR last_read_addr compare mismatch act * != exp *
spi_device_flash_and_tpm 86111161785935336610045035793802907929123873640806510235857070106622139745688 101
tl_ul_fuzzy_flash_status_q[i] = 0x87442c
UVM_INFO @ 4473564270 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 6/6
UVM_INFO @ 4645738270 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 4/5
UVM_INFO @ 5030284270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]