Simulation Results: spi_host

 
12/04/2026 00:11:27 DVSim: v1.29.0 sha: 4a305de json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.81 %
  • code
  • 95.03 %
  • assert
  • 95.64 %
  • func
  • 90.76 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.74%
V2S
100.00%
unmapped
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
spi_host_smoke 79.000s 22752.032us 50 50 100.00
csr_hw_reset 5 5 100.00
spi_host_csr_hw_reset 23.000s 34.150us 5 5 100.00
csr_rw 20 20 100.00
spi_host_csr_rw 24.000s 29.287us 20 20 100.00
csr_bit_bash 5 5 100.00
spi_host_csr_bit_bash 25.000s 196.510us 5 5 100.00
csr_aliasing 5 5 100.00
spi_host_csr_aliasing 24.000s 21.784us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
spi_host_csr_mem_rw_with_rand_reset 24.000s 77.833us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
spi_host_csr_rw 24.000s 29.287us 20 20 100.00
spi_host_csr_aliasing 24.000s 21.784us 5 5 100.00
mem_walk 5 5 100.00
spi_host_mem_walk 23.000s 113.828us 5 5 100.00
mem_partial_access 5 5 100.00
spi_host_mem_partial_access 23.000s 15.968us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 50 50 100.00
spi_host_performance 21.000s 20.859us 50 50 100.00
error_event_intr 150 150 100.00
spi_host_overflow_underflow 26.000s 368.635us 50 50 100.00
spi_host_error_cmd 24.000s 18.712us 50 50 100.00
spi_host_event 598.000s 19333.452us 50 50 100.00
clock_rate 50 50 100.00
spi_host_speed 17.000s 68.251us 50 50 100.00
speed 50 50 100.00
spi_host_speed 17.000s 68.251us 50 50 100.00
chip_select_timing 50 50 100.00
spi_host_speed 17.000s 68.251us 50 50 100.00
sw_reset 50 50 100.00
spi_host_sw_reset 131.000s 5136.547us 50 50 100.00
passthrough_mode 50 50 100.00
spi_host_passthrough_mode 23.000s 31.018us 50 50 100.00
cpol_cpha 50 50 100.00
spi_host_speed 17.000s 68.251us 50 50 100.00
full_cycle 50 50 100.00
spi_host_speed 17.000s 68.251us 50 50 100.00
duplex 50 50 100.00
spi_host_smoke 79.000s 22752.032us 50 50 100.00
tx_rx_only 50 50 100.00
spi_host_smoke 79.000s 22752.032us 50 50 100.00
stress_all 48 50 96.00
spi_host_stress_all 1721.000s 1000000.000us 48 50 96.00
spien 50 50 100.00
spi_host_spien 187.000s 11291.383us 50 50 100.00
stall 50 50 100.00
spi_host_status_stall 1136.000s 335044.261us 50 50 100.00
Idlecsbactive 50 50 100.00
spi_host_idlecsbactive 24.000s 66.216us 50 50 100.00
data_fifo_status 50 50 100.00
spi_host_overflow_underflow 26.000s 368.635us 50 50 100.00
alert_test 50 50 100.00
spi_host_alert_test 23.000s 15.487us 50 50 100.00
intr_test 50 50 100.00
spi_host_intr_test 24.000s 35.423us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
spi_host_tl_errors 10.000s 107.514us 20 20 100.00
tl_d_illegal_access 20 20 100.00
spi_host_tl_errors 10.000s 107.514us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
spi_host_csr_hw_reset 23.000s 34.150us 5 5 100.00
spi_host_csr_rw 24.000s 29.287us 20 20 100.00
spi_host_csr_aliasing 24.000s 21.784us 5 5 100.00
spi_host_same_csr_outstanding 21.000s 25.021us 20 20 100.00
tl_d_partial_access 50 50 100.00
spi_host_csr_hw_reset 23.000s 34.150us 5 5 100.00
spi_host_csr_rw 24.000s 29.287us 20 20 100.00
spi_host_csr_aliasing 24.000s 21.784us 5 5 100.00
spi_host_same_csr_outstanding 21.000s 25.021us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
spi_host_tl_intg_err 7.000s 170.859us 20 20 100.00
spi_host_sec_cm 20.000s 70.990us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
spi_host_tl_intg_err 7.000s 170.859us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 9 10 90.00
spi_host_upper_range_clkdiv 518.000s 56289.937us 9 10 90.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
spi_host_stress_all 14171504032235306502957768302938156163619963277793900370549577742871709181352 159
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
spi_host_upper_range_clkdiv 1525774593020302922772856798296108195636366174088563844209581211139904545268 136
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.rxqd (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=*
spi_host_stress_all 57998429784963996579309955801914543155726038278577963819427030091223550864082 204
UVM_INFO @ 10072604285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---