Simulation Results: sram_ctrl/main

 
12/04/2026 00:11:27 DVSim: v1.29.0 sha: 4a305de json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.71 %
  • code
  • 95.87 %
  • assert
  • 95.92 %
  • func
  • 98.33 %
  • line
  • 99.16 %
  • branch
  • 98.14 %
  • cond
  • 92.18 %
  • toggle
  • 89.85 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
98.63%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
sram_ctrl_smoke 90.400s 13227.798us 50 50 100.00
csr_hw_reset 5 5 100.00
sram_ctrl_csr_hw_reset 1.020s 26.638us 5 5 100.00
csr_rw 20 20 100.00
sram_ctrl_csr_rw 1.090s 19.853us 20 20 100.00
csr_bit_bash 5 5 100.00
sram_ctrl_csr_bit_bash 2.810s 688.837us 5 5 100.00
csr_aliasing 5 5 100.00
sram_ctrl_csr_aliasing 1.090s 17.781us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 5.720s 2125.874us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sram_ctrl_csr_rw 1.090s 19.853us 20 20 100.00
sram_ctrl_csr_aliasing 1.090s 17.781us 5 5 100.00
mem_walk 50 50 100.00
sram_ctrl_mem_walk 334.130s 230858.290us 50 50 100.00
mem_partial_access 50 50 100.00
sram_ctrl_mem_partial_access 171.590s 5927.586us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 50 50 100.00
sram_ctrl_multiple_keys 1542.610s 36325.297us 50 50 100.00
stress_pipeline 50 50 100.00
sram_ctrl_stress_pipeline 397.900s 25766.803us 50 50 100.00
bijection 50 50 100.00
sram_ctrl_bijection 2225.070s 244744.528us 50 50 100.00
access_during_key_req 50 50 100.00
sram_ctrl_access_during_key_req 1199.700s 21154.430us 50 50 100.00
lc_escalation 50 50 100.00
sram_ctrl_lc_escalation 129.640s 83423.448us 50 50 100.00
executable 50 50 100.00
sram_ctrl_executable 1738.880s 85934.809us 50 50 100.00
partial_access 100 100 100.00
sram_ctrl_partial_access 100.680s 5639.346us 50 50 100.00
sram_ctrl_partial_access_b2b 548.250s 32395.753us 50 50 100.00
max_throughput 150 150 100.00
sram_ctrl_max_throughput 112.400s 1540.665us 50 50 100.00
sram_ctrl_throughput_w_partial_write 95.240s 802.923us 50 50 100.00
sram_ctrl_throughput_w_readback 111.200s 3654.819us 50 50 100.00
regwen 50 50 100.00
sram_ctrl_regwen 1640.260s 106332.009us 50 50 100.00
ram_cfg 50 50 100.00
sram_ctrl_ram_cfg 6.250s 5559.402us 50 50 100.00
stress_all 50 50 100.00
sram_ctrl_stress_all 9147.830s 2218853.046us 50 50 100.00
alert_test 50 50 100.00
sram_ctrl_alert_test 1.060s 161.790us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sram_ctrl_tl_errors 5.740s 186.364us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sram_ctrl_tl_errors 5.740s 186.364us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.020s 26.638us 5 5 100.00
sram_ctrl_csr_rw 1.090s 19.853us 20 20 100.00
sram_ctrl_csr_aliasing 1.090s 17.781us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.150s 22.127us 20 20 100.00
tl_d_partial_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.020s 26.638us 5 5 100.00
sram_ctrl_csr_rw 1.090s 19.853us 20 20 100.00
sram_ctrl_csr_aliasing 1.090s 17.781us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.150s 22.127us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 65.650s 28234.636us 20 20 100.00
tl_intg_err 20 25 80.00
sram_ctrl_sec_cm 0.940s 3.994us 0 5 0.00
sram_ctrl_tl_intg_err 3.400s 722.892us 20 20 100.00
prim_count_check 0 5 0.00
sram_ctrl_sec_cm 0.940s 3.994us 0 5 0.00
sec_cm_bus_integrity 20 20 100.00
sram_ctrl_tl_intg_err 3.400s 722.892us 20 20 100.00
sec_cm_ctrl_config_regwen 50 50 100.00
sram_ctrl_regwen 1640.260s 106332.009us 50 50 100.00
sec_cm_readback_config_regwen 50 50 100.00
sram_ctrl_regwen 1640.260s 106332.009us 50 50 100.00
sec_cm_exec_config_regwen 20 20 100.00
sram_ctrl_csr_rw 1.090s 19.853us 20 20 100.00
sec_cm_exec_config_mubi 50 50 100.00
sram_ctrl_executable 1738.880s 85934.809us 50 50 100.00
sec_cm_exec_intersig_mubi 50 50 100.00
sram_ctrl_executable 1738.880s 85934.809us 50 50 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 50 50 100.00
sram_ctrl_executable 1738.880s 85934.809us 50 50 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
sram_ctrl_lc_escalation 129.640s 83423.448us 50 50 100.00
sec_cm_prim_ram_ctrl_mubi 50 50 100.00
sram_ctrl_mubi_enc_err 11.010s 11091.170us 50 50 100.00
sec_cm_mem_integrity 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 65.650s 28234.636us 20 20 100.00
sec_cm_mem_readback 50 50 100.00
sram_ctrl_readback_err 11.750s 9409.386us 50 50 100.00
sec_cm_mem_scramble 50 50 100.00
sram_ctrl_smoke 90.400s 13227.798us 50 50 100.00
sec_cm_addr_scramble 50 50 100.00
sram_ctrl_smoke 90.400s 13227.798us 50 50 100.00
sec_cm_instr_bus_lc_gated 50 50 100.00
sram_ctrl_executable 1738.880s 85934.809us 50 50 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 5 0.00
sram_ctrl_sec_cm 0.940s 3.994us 0 5 0.00
sec_cm_key_global_esc 50 50 100.00
sram_ctrl_lc_escalation 129.640s 83423.448us 50 50 100.00
sec_cm_key_local_esc 0 5 0.00
sram_ctrl_sec_cm 0.940s 3.994us 0 5 0.00
sec_cm_init_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 0.940s 3.994us 0 5 0.00
sec_cm_scramble_key_sideload 50 50 100.00
sram_ctrl_smoke 90.400s 13227.798us 50 50 100.00
sec_cm_tlul_fifo_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 0.940s 3.994us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
sram_ctrl_stress_all_with_rand_reset 296.360s 11355.852us 50 50 100.00

Error Messages

   Test seed line log context
Offending '(!$isunknown(rdata_o))'
sram_ctrl_sec_cm 5507213402288337076625737459725181885672578584871037378533801624162721364429 99
UVM_ERROR @ 6407000 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 6407000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 8863359808745795450935131855974307909089766358535470878473831370998369696305 99
UVM_INFO @ 6266155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 49117938730378250906219225118305494352730470588469122627688627946189640169348 100
UVM_INFO @ 5143451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(depth_o <= *'(Depth))'
sram_ctrl_sec_cm 23578971227964611326459674959905565152046866352410549252962036719155527836445 104
UVM_ERROR @ 4140155 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
UVM_INFO @ 4140155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 31054648328191134917280725699380323356598377631094920424777506706806620054312 99
UVM_ERROR @ 3993812 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
UVM_INFO @ 3993812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---