| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 5 | 5 | 100.00 | |||
| aon_timer_smoke | 1.070s | 733.662us | 5 | 5 | 100.00 | |
| csr_hw_reset | 5 | 5 | 100.00 | |||
| aon_timer_csr_hw_reset | 2.060s | 1170.443us | 5 | 5 | 100.00 | |
| csr_rw | 20 | 20 | 100.00 | |||
| aon_timer_csr_rw | 1.250s | 370.528us | 20 | 20 | 100.00 | |
| csr_bit_bash | 5 | 5 | 100.00 | |||
| aon_timer_csr_bit_bash | 20.800s | 11604.665us | 5 | 5 | 100.00 | |
| csr_aliasing | 5 | 5 | 100.00 | |||
| aon_timer_csr_aliasing | 1.530s | 682.570us | 5 | 5 | 100.00 | |
| csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 | |||
| aon_timer_csr_mem_rw_with_rand_reset | 1.260s | 505.795us | 20 | 20 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 25 | 25 | 100.00 | |||
| aon_timer_csr_rw | 1.250s | 370.528us | 20 | 20 | 100.00 | |
| aon_timer_csr_aliasing | 1.530s | 682.570us | 5 | 5 | 100.00 | |
| mem_walk | 5 | 5 | 100.00 | |||
| aon_timer_mem_walk | 1.150s | 412.874us | 5 | 5 | 100.00 | |
| mem_partial_access | 5 | 5 | 100.00 | |||
| aon_timer_mem_partial_access | 1.100s | 298.915us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| prescaler | 15 | 15 | 100.00 | |||
| aon_timer_prescaler | 27.910s | 23939.404us | 15 | 15 | 100.00 | |
| jump | 5 | 5 | 100.00 | |||
| aon_timer_jump | 1.400s | 669.876us | 5 | 5 | 100.00 | |
| stress_all | 15 | 15 | 100.00 | |||
| aon_timer_stress_all | 155.040s | 113924.756us | 15 | 15 | 100.00 | |
| alert_test | 50 | 50 | 100.00 | |||
| aon_timer_alert_test | 1.380s | 343.234us | 50 | 50 | 100.00 | |
| intr_test | 50 | 50 | 100.00 | |||
| aon_timer_intr_test | 1.110s | 460.700us | 50 | 50 | 100.00 | |
| tl_d_oob_addr_access | 20 | 20 | 100.00 | |||
| aon_timer_tl_errors | 2.280s | 834.431us | 20 | 20 | 100.00 | |
| tl_d_illegal_access | 20 | 20 | 100.00 | |||
| aon_timer_tl_errors | 2.280s | 834.431us | 20 | 20 | 100.00 | |
| tl_d_outstanding_access | 50 | 50 | 100.00 | |||
| aon_timer_csr_hw_reset | 2.060s | 1170.443us | 5 | 5 | 100.00 | |
| aon_timer_csr_rw | 1.250s | 370.528us | 20 | 20 | 100.00 | |
| aon_timer_csr_aliasing | 1.530s | 682.570us | 5 | 5 | 100.00 | |
| aon_timer_same_csr_outstanding | 5.430s | 2722.427us | 20 | 20 | 100.00 | |
| tl_d_partial_access | 50 | 50 | 100.00 | |||
| aon_timer_csr_hw_reset | 2.060s | 1170.443us | 5 | 5 | 100.00 | |
| aon_timer_csr_rw | 1.250s | 370.528us | 20 | 20 | 100.00 | |
| aon_timer_csr_aliasing | 1.530s | 682.570us | 5 | 5 | 100.00 | |
| aon_timer_same_csr_outstanding | 5.430s | 2722.427us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 25 | 25 | 100.00 | |||
| aon_timer_sec_cm | 10.460s | 8250.851us | 5 | 5 | 100.00 | |
| aon_timer_tl_intg_err | 10.660s | 8033.731us | 20 | 20 | 100.00 | |
| sec_cm_bus_integrity | 20 | 20 | 100.00 | |||
| aon_timer_tl_intg_err | 10.660s | 8033.731us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| max_threshold | 5 | 5 | 100.00 | |||
| aon_timer_smoke_max_thold | 1.470s | 655.094us | 5 | 5 | 100.00 | |
| min_threshold | 5 | 5 | 100.00 | |||
| aon_timer_smoke_min_thold | 1.070s | 485.715us | 5 | 5 | 100.00 | |
| wkup_count_hi_cdc | 5 | 5 | 100.00 | |||
| aon_timer_wkup_count_cdc_hi | 6.730s | 3770.716us | 5 | 5 | 100.00 | |
| custom_intr | 10 | 10 | 100.00 | |||
| aon_timer_custom_intr | 1.410s | 678.473us | 10 | 10 | 100.00 | |
| alternating_on_off | 5 | 5 | 100.00 | |||
| aon_timer_alternating_enable_on_off | 12.320s | 4127.663us | 5 | 5 | 100.00 | |
| stress_all_with_rand_reset | 15 | 15 | 100.00 | |||
| aon_timer_stress_all_with_rand_reset | 31.930s | 8719.881us | 15 | 15 | 100.00 | |