Simulation Results: csrng

 
25/04/2026 09:02:00 DVSim: v1.17.3 sha: 8007f61 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.27 %
  • code
  • 96.23 %
  • assert
  • 95.85 %
  • func
  • 90.74 %
  • block
  • 98.59 %
  • line
  • 99.57 %
  • branch
  • 96.46 %
  • toggle
  • 93.64 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
96.67%
V2S
99.78%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
csrng_smoke 5.000s 169.952us 50 50 100.00
csr_hw_reset 5 5 100.00
csrng_csr_hw_reset 5.000s 292.913us 5 5 100.00
csr_rw 20 20 100.00
csrng_csr_rw 3.000s 15.117us 20 20 100.00
csr_bit_bash 5 5 100.00
csrng_csr_bit_bash 23.000s 1592.068us 5 5 100.00
csr_aliasing 5 5 100.00
csrng_csr_aliasing 4.000s 103.643us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
csrng_csr_mem_rw_with_rand_reset 3.000s 56.494us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
csrng_csr_rw 3.000s 15.117us 20 20 100.00
csrng_csr_aliasing 4.000s 103.643us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 200 200 100.00
csrng_intr 20.000s 1055.038us 200 200 100.00
alerts 500 500 100.00
csrng_alert 62.000s 4126.067us 500 500 100.00
err 500 500 100.00
csrng_err 4.000s 164.562us 500 500 100.00
cmds 4 50 8.00
csrng_cmds 23.000s 1853.999us 4 50 8.00
life cycle 4 50 8.00
csrng_cmds 23.000s 1853.999us 4 50 8.00
stress_all 47 50 94.00
csrng_stress_all 1317.000s 102374.584us 47 50 94.00
intr_test 50 50 100.00
csrng_intr_test 3.000s 50.623us 50 50 100.00
alert_test 50 50 100.00
csrng_alert_test 4.000s 178.691us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
csrng_tl_errors 12.000s 868.767us 20 20 100.00
tl_d_illegal_access 20 20 100.00
csrng_tl_errors 12.000s 868.767us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
csrng_csr_hw_reset 5.000s 292.913us 5 5 100.00
csrng_csr_rw 3.000s 15.117us 20 20 100.00
csrng_csr_aliasing 4.000s 103.643us 5 5 100.00
csrng_same_csr_outstanding 4.000s 54.737us 20 20 100.00
tl_d_partial_access 50 50 100.00
csrng_csr_hw_reset 5.000s 292.913us 5 5 100.00
csrng_csr_rw 3.000s 15.117us 20 20 100.00
csrng_csr_aliasing 4.000s 103.643us 5 5 100.00
csrng_same_csr_outstanding 4.000s 54.737us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
csrng_sec_cm 7.000s 804.156us 5 5 100.00
csrng_tl_intg_err 7.000s 187.216us 20 20 100.00
sec_cm_config_regwen 70 70 100.00
csrng_regwen 4.000s 133.532us 50 50 100.00
csrng_csr_rw 3.000s 15.117us 20 20 100.00
sec_cm_config_mubi 500 500 100.00
csrng_alert 62.000s 4126.067us 500 500 100.00
sec_cm_intersig_mubi 47 50 94.00
csrng_stress_all 1317.000s 102374.584us 47 50 94.00
sec_cm_main_sm_fsm_sparse 705 705 100.00
csrng_intr 20.000s 1055.038us 200 200 100.00
csrng_err 4.000s 164.562us 500 500 100.00
csrng_sec_cm 7.000s 804.156us 5 5 100.00
sec_cm_cmd_stage_fsm_sparse 705 705 100.00
csrng_intr 20.000s 1055.038us 200 200 100.00
csrng_err 4.000s 164.562us 500 500 100.00
csrng_sec_cm 7.000s 804.156us 5 5 100.00
sec_cm_ctr_drbg_fsm_sparse 705 705 100.00
csrng_intr 20.000s 1055.038us 200 200 100.00
csrng_err 4.000s 164.562us 500 500 100.00
csrng_sec_cm 7.000s 804.156us 5 5 100.00
sec_cm_ctr_drbg_ctr_redun 705 705 100.00
csrng_intr 20.000s 1055.038us 200 200 100.00
csrng_err 4.000s 164.562us 500 500 100.00
csrng_sec_cm 7.000s 804.156us 5 5 100.00
sec_cm_gen_cmd_ctr_redun 705 705 100.00
csrng_intr 20.000s 1055.038us 200 200 100.00
csrng_err 4.000s 164.562us 500 500 100.00
csrng_sec_cm 7.000s 804.156us 5 5 100.00
sec_cm_ctrl_mubi 500 500 100.00
csrng_alert 62.000s 4126.067us 500 500 100.00
sec_cm_main_sm_ctr_local_esc 700 700 100.00
csrng_intr 20.000s 1055.038us 200 200 100.00
csrng_err 4.000s 164.562us 500 500 100.00
sec_cm_constants_lc_gated 47 50 94.00
csrng_stress_all 1317.000s 102374.584us 47 50 94.00
sec_cm_sw_genbits_bus_consistency 500 500 100.00
csrng_alert 62.000s 4126.067us 500 500 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
csrng_tl_intg_err 7.000s 187.216us 20 20 100.00
sec_cm_aes_cipher_fsm_sparse 705 705 100.00
csrng_intr 20.000s 1055.038us 200 200 100.00
csrng_err 4.000s 164.562us 500 500 100.00
csrng_sec_cm 7.000s 804.156us 5 5 100.00
sec_cm_aes_cipher_fsm_redun 700 700 100.00
csrng_intr 20.000s 1055.038us 200 200 100.00
csrng_err 4.000s 164.562us 500 500 100.00
sec_cm_aes_cipher_ctrl_sparse 700 700 100.00
csrng_intr 20.000s 1055.038us 200 200 100.00
csrng_err 4.000s 164.562us 500 500 100.00
sec_cm_aes_cipher_fsm_local_esc 700 700 100.00
csrng_intr 20.000s 1055.038us 200 200 100.00
csrng_err 4.000s 164.562us 500 500 100.00
sec_cm_aes_cipher_ctr_redun 705 705 100.00
csrng_intr 20.000s 1055.038us 200 200 100.00
csrng_err 4.000s 164.562us 500 500 100.00
csrng_sec_cm 7.000s 804.156us 5 5 100.00
sec_cm_aes_cipher_data_reg_local_esc 700 700 100.00
csrng_intr 20.000s 1055.038us 200 200 100.00
csrng_err 4.000s 164.562us 500 500 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 10 0.00
csrng_stress_all_with_rand_reset 0.000s 0.000us 0 10 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes
csrng_stress_all_with_rand_reset 98313865236331053045552394141389176881237205411672772050609910698604175513905 None
Job timed out after 180 minutes
csrng_stress_all_with_rand_reset 35776092119716348875227556509055045251302742205750709590713541617231239894397 None
Job timed out after 180 minutes
csrng_stress_all_with_rand_reset 17770391777932009421465275363489634709608871228376775605387521965449067554939 None
Job timed out after 180 minutes
csrng_stress_all_with_rand_reset 67739076142195184066851386216714039700009973234083888106752874942399214402363 None
Job timed out after 180 minutes
csrng_stress_all_with_rand_reset 110020890680402040399212770673959395473686047676961595606348416994195799985573 None
Job timed out after 180 minutes
csrng_stress_all_with_rand_reset 52641555098731675986478573925689604493555487991381532831175560472325518143144 None
Job timed out after 180 minutes
csrng_stress_all_with_rand_reset 80170623198206280862738719751904044026501691654763218203434275262767747151811 None
Job timed out after 180 minutes
csrng_stress_all_with_rand_reset 54595591838877168177334819552578568958017808232539940385525090215710211190003 None
Job timed out after 180 minutes
csrng_stress_all_with_rand_reset 39052673583362233617469421659415268360674718865608448698422242444815712891009 None
Job timed out after 180 minutes
csrng_stress_all_with_rand_reset 111869698590185777426934386043634796099226348902934200037891360657737067840427 None
Job timed out after 180 minutes
UVM_FATAL (csrng_scoreboard.sv:660) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*])
csrng_cmds 3467800020108578610100797578337538809277639173967509953412865333569149825231 130
UVM_FATAL @ 83227289 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 75865318419012738790078671492711525648 [0x391320fc34d9734a95a1806964dd2d10])
UVM_INFO @ 83227289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 35145238530592015280280347438997328998504626808906047620678235552807016445672 130
UVM_FATAL @ 39152089 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 106625393045475032586788375836922883913 [0x50374dc13d075fde2fc5f3e34f322f49])
UVM_INFO @ 39152089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 12894906173426453091993829538240408085675731610609536644083988892807234341626 130
UVM_FATAL @ 143537123 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 255446168248543645180558855610596846890 [0xc02d2478510a19dbd271d33260cbed2a])
UVM_INFO @ 143537123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 50732635258001777884071902819732315019083398778665886958766121537763926006365 140
UVM_FATAL @ 152771658 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 92963669207548193370345058238595605750 [0x45f026c3e654c05e6efcb1ec0b7824f6])
UVM_INFO @ 152771658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 66195623184435204657641463142247121359641740372661876871004031616017917810536 130
UVM_FATAL @ 66188785 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 99916317928012715565333948255354912327 [0x4b2b2ed01cd89e762a435446425e7e47])
UVM_INFO @ 66188785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 54216453913553957776516168158073726581098344213610359562974382094572740095132 130
UVM_FATAL @ 5966372 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 265722521609922856047835277817285778074 [0xc7e84bcef4ff1f22d697d595f8711a9a])
UVM_INFO @ 5966372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 51642914640660378651632122622257290122092744515489258858916543593108471058458 130
UVM_FATAL @ 140209100 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 323158490337953845361417808614568850856 [0xf31e0fb37c545650244188b3ca9d75a8])
UVM_INFO @ 140209100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 16366779513064905220831448001808977032590288579892488701680321321174476636655 130
UVM_FATAL @ 179027030 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 326129643910079250768943480902438510653 [0xf55a48e1d4382573c595d0b17d76603d])
UVM_INFO @ 179027030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 95151871558620110311491135732170813081737576042576326810259766170027918409033 130
UVM_FATAL @ 816450394 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 82369016409871233761531265186434138321 [0x3df7b20d8e5bacf4d1e1dcfef5d440d1])
UVM_INFO @ 816450394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 41400184202154772162612385280049025425637027589090086551108954869135453180930 130
UVM_FATAL @ 116763730 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 98086522628005155172964387834746537498 [0x49cac6f07c25b6d1e652585252d6861a])
UVM_INFO @ 116763730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 85480283861895340560214041125809530823406872962420943646643766353419814517057 130
UVM_FATAL @ 114386988 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 93870077091890034817773054320146170420 [0x469eb81fce55879b2a7c5c7929c8c234])
UVM_INFO @ 114386988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 66249657027516550991455540347991906760324346376212272765907547025411806158910 130
UVM_FATAL @ 311538184 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 83866080763982530256584768571820163358 [0x3f1805063894c2b566372b805067411e])
UVM_INFO @ 311538184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 59094093742354944978981219699284018950692737069057642819167070635486861374422 130
UVM_FATAL @ 581328302 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 254958888327607581770079198840785572674 [0xbfcf4bb70b4d6acc9295c473e68d9342])
UVM_INFO @ 581328302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 95180113417810363472953895916602160892101010604103771226006100135496178503523 130
UVM_FATAL @ 35257661 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 54343862641041938856489170722428711787 [0x28e23f4ad1caaad43b110f00c682736b])
UVM_INFO @ 35257661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 255016786881152001268914161485827679174517796174334216527571878954065273620 130
UVM_FATAL @ 531912648 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 21894711803957174505913570299038055829 [0x1078c4a2c5854d1ad2513e6d9986bd95])
UVM_INFO @ 531912648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 52326014853458227518077797045806221588662037002897258879716298543488873601718 130
UVM_FATAL @ 388473888 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 224994036452933474885739372101614392972 [0xa94446743fdbbff249b98bcc9783568c])
UVM_INFO @ 388473888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 103257949373962028707316874316856610589707967175845037166836159224026305131790 130
UVM_FATAL @ 95516577 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 81588543251040316254459835031176905456 [0x3d6161c15ad8b886c31643c38b4c82f0])
UVM_INFO @ 95516577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 6445083065550743079195350431147503572290021966675036779610846992365433786981 130
UVM_FATAL @ 103861206 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 23370719058794480339873729261212838679 [0x119509697a6a562ec12599aa03e0ab17])
UVM_INFO @ 103861206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 89669626684654073025868651557687057892860949252435670171325363877794777836663 139
UVM_FATAL @ 28421816 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 308192851706153810706358632036240226292 [0xe7dbc8bfac48bac0551e77e5a63477f4])
UVM_INFO @ 28421816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 42629619110754579232818879917799915847206527708595429203065547370895470294638 130
UVM_FATAL @ 179428402 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 15156290491846631600821440508752753216 [0xb66fed09855536978345d11f512f240])
UVM_INFO @ 179428402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 109975284168426140929477549190009535742928006295644726924146948597593410337524 130
UVM_FATAL @ 108924635 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 244324928037978408021433341540952455317 [0xb7cf44fe66cd62ba58b62b9c0b183895])
UVM_INFO @ 108924635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 59603198298033924173120043548159579351790331463951922539034375595723239933441 139
UVM_FATAL @ 17641932 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 298298747113967466707281060648954412244 [0xe06a3fbacb3c4e2e341b78cca4b0bcd4])
UVM_INFO @ 17641932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 104792645703262798378477504944661583283133966803015146451228950884980489229220 130
UVM_FATAL @ 82893311 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 112564702710524304955781114154929183557 [0x54af2c546b24f30086e4af0dc1a15b45])
UVM_INFO @ 82893311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 100686331158971920051672192082724578207891213057444000538559332878102283613096 130
UVM_FATAL @ 169725212 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 168126369257531609015072549635940608833 [0x7e7bf5fd8119845c0b8cc5dbf34eeb41])
UVM_INFO @ 169725212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 32584703575515651129202182049547011951195768870783616519482302445209633994574 140
UVM_FATAL @ 286752786 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 104412577080432472196917152957227091616 [0x4e8d2181277059adb233ebba6bc846a0])
UVM_INFO @ 286752786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 60439615392742206666206082196906386269768170123742705599500715208860994282081 140
UVM_FATAL @ 151650995 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 133431915674736443323762229886416706570 [0x64620d5c8d806d1bde594711f319dc0a])
UVM_INFO @ 151650995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 20775960089391334387210077042759992558259705208627072579324151884218237720047 130
UVM_FATAL @ 72457029 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 329256402935078281418314025730118463250 [0xf7b47a011b5c8d52b454928872f32f12])
UVM_INFO @ 72457029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 1552272766486446967012414648222072672037005280565942978933142238299270650278 130
UVM_FATAL @ 307240982 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 239255348332902034124850847025323153950 [0xb3fee76aa345e9ced9a359c05a459a1e])
UVM_INFO @ 307240982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 83080724322666710819296881303051689534143514597618989040714854083196550177236 130
UVM_FATAL @ 368704707 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 231574544081580198752430824637881618622 [0xae37a28786819e4fb8d0c6c9ceeb90be])
UVM_INFO @ 368704707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 54239592957709669554472282468047019122586580055106191403127977224282796525727 130
UVM_FATAL @ 59040322 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 284318062851212425077147881978733685684 [0xd5e5aac6e7641dae3c36fd9047ce6bb4])
UVM_INFO @ 59040322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 52361433601385139020051185821260040196980229070228933484421317903968021866485 130
UVM_FATAL @ 148387388 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 137546239357250840648811231757168543114 [0x677a712e39c81d2b76901892e0ac058a])
UVM_INFO @ 148387388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 66806465159790983567373261260588207296581770906637941091812864963226004686297 140
UVM_FATAL @ 645326750 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 145087872633088455699837000890176441209 [0x6d26e868abbdc4e3191d4dc1bc130b79])
UVM_INFO @ 645326750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 8528762338398189039149048639688567443054358016267167244968708334560417062176 130
UVM_FATAL @ 64036647 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 62109912996626291714661832735027147835 [0x2eb9ef230914973740454c0aeeccb43b])
UVM_INFO @ 64036647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 66556684470245551401254686670065989620897715411005109912395057293736599166450 130
UVM_FATAL @ 420155143 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 163110333101090466427194217066529242693 [0x7ab5e850562065ed17ec91ff70d73e45])
UVM_INFO @ 420155143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 49517226458890001759227619714796321900860390055440758265610139253321597861904 130
UVM_FATAL @ 41099282 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 69080342441454604338420283710600334508 [0x33f863d78a9f55bf0f4cdd93ccbf4cac])
UVM_INFO @ 41099282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 26493345068805530634975394205259796882849280748986757907094536205199504736010 130
UVM_FATAL @ 70219293 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 296140689775667937371178734959048716591 [0xdeca9f49bf5124ed3c36fd0a0f96f12f])
UVM_INFO @ 70219293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 13074715500543924635008918424078007125514762785403010725239271452658073461879 130
UVM_FATAL @ 149187130 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 152636118720139652214492137640192060510 [0x72d4a5ac8721c5a7212ff358e0572c5e])
UVM_INFO @ 149187130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 47783149275062520890415597854654052397247369777307887297041389049590451991171 140
UVM_FATAL @ 319075898 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 20891082300824828194412463508606143049 [0xfb779e1849bff0468a03fd5b08fca49])
UVM_INFO @ 319075898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 68403645947694252113940473568875974412347006760348223772780580424230576700736 149
UVM_FATAL @ 121194760 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 206472918761444409264759043293676649608 [0x9b553cd9907f1b4d299b54c2517d3c88])
UVM_INFO @ 121194760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 14190226914886077759143437133653685135675424113782464237797805951308411849605 130
UVM_FATAL @ 170727191 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 90689403423001978427011716161004505195 [0x443a24ce0d336bda82d5663bbada086b])
UVM_INFO @ 170727191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_scoreboard.sv:629) [scoreboard] Check failed cs_item[app].status == cmd_sts[app] (* [*] vs * [*])
csrng_cmds 1613003467554977747617460828158809112876552813116657110356979556250668944125 149
UVM_FATAL @ 1853999183 ps: (csrng_scoreboard.sv:629) [uvm_test_top.env.scoreboard] Check failed cs_item[app].status == cmd_sts[app] (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1853999183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 100018669630535901505123968394088185822845357977345522261398528335815931737628 139
UVM_FATAL @ 114304012 ps: (csrng_scoreboard.sv:629) [uvm_test_top.env.scoreboard] Check failed cs_item[app].status == cmd_sts[app] (0 [0x0] vs 3 [0x3])
UVM_INFO @ 114304012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 37417551024410291584952804527609101905124181034332354999862682736895480081277 139
UVM_FATAL @ 196857149 ps: (csrng_scoreboard.sv:629) [uvm_test_top.env.scoreboard] Check failed cs_item[app].status == cmd_sts[app] (0 [0x0] vs 3 [0x3])
UVM_INFO @ 196857149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 59472532497477563433307461683744485133487584210527692697499434469554581891528 139
UVM_FATAL @ 16235459 ps: (csrng_scoreboard.sv:629) [uvm_test_top.env.scoreboard] Check failed cs_item[app].status == cmd_sts[app] (0 [0x0] vs 3 [0x3])
UVM_INFO @ 16235459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 95270432984326257689207533400125603620080035102562798158184109900374891791452 139
UVM_FATAL @ 20944610 ps: (csrng_scoreboard.sv:629) [uvm_test_top.env.scoreboard] Check failed cs_item[app].status == cmd_sts[app] (0 [0x0] vs 3 [0x3])
UVM_INFO @ 20944610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq
csrng_stress_all 109376535905334247391418269303900362079531382904566251891822762636970366076132 174
UVM_ERROR @ 17417276446 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 17417276446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all 10812106976235748534082041645266189929560586286469684204870855747716082417364 145
UVM_ERROR @ 1978683445 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 1978683445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all 11623680874602402886603045583451202180480925987461058780322358090099784111847 148
UVM_ERROR @ 3619650944 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 3619650944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:418) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: csrng_reg_block.genbits
csrng_cmds 50884924501948700038575944283055645063547644655233314764971409703046391190781 133
UVM_ERROR @ 81139522 ps: (csrng_scoreboard.sv:418) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3718475525 [0xdda36f05] vs 0 [0x0]) reg name: csrng_reg_block.genbits
UVM_INFO @ 81139522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---