Simulation Results

Simulation Results: flash_ctrl

25/04/2026 09:02:00 DVSim: v1.17.3 sha: 8007f61 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
96.96 %

code
95.77 %

assert
96.76 %

func
98.36 %

line
96.10 %

branch
97.42 %

cond
94.82 %

toggle
98.66 %

FSM
91.84 %

Validation stages

V1		100.00%
V2		98.37%
V2S		97.94%
V3		100.00%
unmapped		100.00%

120/120 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	flash_ctrl_smoke	144.840s	126.326us	50	50	100.00
smoke_hw				5	5	100.00
	flash_ctrl_smoke_hw	24.830s	51.128us	5	5	100.00
csr_hw_reset				5	5	100.00
	flash_ctrl_csr_hw_reset	33.130s	26.323us	5	5	100.00
csr_rw				20	20	100.00
	flash_ctrl_csr_rw	18.780s	26.854us	20	20	100.00
csr_bit_bash				5	5	100.00
	flash_ctrl_csr_bit_bash	63.680s	6178.777us	5	5	100.00
csr_aliasing				5	5	100.00
	flash_ctrl_csr_aliasing	47.340s	460.578us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	flash_ctrl_csr_mem_rw_with_rand_reset	18.110s	94.860us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	flash_ctrl_csr_rw	18.780s	26.854us	20	20	100.00
	flash_ctrl_csr_aliasing	47.340s	460.578us	5	5	100.00
mem_walk				5	5	100.00
	flash_ctrl_mem_walk	13.350s	42.562us	5	5	100.00
mem_partial_access				5	5	100.00
	flash_ctrl_mem_partial_access	13.600s	54.764us	5	5	100.00

1026/1043 passed

98.37 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
sw_op				5	5	100.00
	flash_ctrl_sw_op	25.650s	27.108us	5	5	100.00
host_read_direct				5	5	100.00
	flash_ctrl_host_dir_rd	63.440s	151.249us	5	5	100.00
rma_hw_if				43	43	100.00
	flash_ctrl_hw_rma	1572.130s	170390.239us	3	3	100.00
	flash_ctrl_hw_rma_reset	869.430s	270240.083us	20	20	100.00
	flash_ctrl_lcmgr_intg	13.280s	60.489us	20	20	100.00
host_controller_arb				5	5	100.00
	flash_ctrl_host_ctrl_arb	1980.720s	283930.977us	5	5	100.00
erase_suspend				5	5	100.00
	flash_ctrl_erase_suspend	321.580s	4377.364us	5	5	100.00
program_reset				30	30	100.00
	flash_ctrl_prog_reset	184.140s	5106.390us	30	30	100.00
full_memory_access				5	5	100.00
	flash_ctrl_full_mem_access	2765.170s	195654.213us	5	5	100.00
rd_buff_eviction				5	5	100.00
	flash_ctrl_rd_buff_evict	178.330s	3310.539us	5	5	100.00
rd_buff_eviction_w_ecc				97	100	97.00
	flash_ctrl_rw_evict	32.160s	72.974us	39	40	97.50
	flash_ctrl_rw_evict_all_en	31.620s	28.119us	38	40	95.00
	flash_ctrl_re_evict	35.080s	142.592us	20	20	100.00
host_arb				20	20	100.00
	flash_ctrl_phy_arb	181.190s	2819.287us	20	20	100.00
host_interleave				20	20	100.00
	flash_ctrl_phy_arb	181.190s	2819.287us	20	20	100.00
memory_protection				20	20	100.00
	flash_ctrl_mp_regions	855.660s	14063.636us	20	20	100.00
fetch_code				10	10	100.00
	flash_ctrl_fetch_code	28.380s	498.268us	10	10	100.00
all_partitions				20	20	100.00
	flash_ctrl_rand_ops	796.950s	309.463us	20	20	100.00
error_mp				10	10	100.00
	flash_ctrl_error_mp	749.920s	6423.140us	10	10	100.00
error_prog_win				10	10	100.00
	flash_ctrl_error_prog_win	572.400s	737.960us	10	10	100.00
error_prog_type				5	5	100.00
	flash_ctrl_error_prog_type	1135.920s	3531.939us	5	5	100.00
error_read_seed				20	20	100.00
	flash_ctrl_hw_read_seed_err	13.510s	23.310us	20	20	100.00
read_write_overflow				5	5	100.00
	flash_ctrl_oversize_error	188.170s	1675.883us	5	5	100.00
flash_ctrl_disable				50	50	100.00
	flash_ctrl_disable	23.090s	59.384us	50	50	100.00
flash_ctrl_connect				80	80	100.00
	flash_ctrl_connect	17.010s	16.250us	80	80	100.00
stress_all				5	5	100.00
	flash_ctrl_stress_all	810.500s	751.256us	5	5	100.00
secret_partition				128	130	98.46
	flash_ctrl_hw_sec_otp	195.710s	13476.553us	50	50	100.00
	flash_ctrl_otp_reset	131.670s	131.052us	78	80	97.50
isolation_partition				3	3	100.00
	flash_ctrl_hw_rma	1572.130s	170390.239us	3	3	100.00
interrupts				98	100	98.00
	flash_ctrl_intr_rd	195.130s	6816.598us	39	40	97.50
	flash_ctrl_intr_wr	79.000s	14463.365us	10	10	100.00
	flash_ctrl_intr_rd_slow_flash	385.260s	12225.595us	40	40	100.00
	flash_ctrl_intr_wr_slow_flash	363.580s	93766.946us	9	10	90.00
invalid_op				20	20	100.00
	flash_ctrl_invalid_op	108.490s	28905.295us	20	20	100.00
mid_op_rst				5	5	100.00
	flash_ctrl_mid_op_rst	78.190s	5482.398us	5	5	100.00
double_bit_err				31	35	88.57
	flash_ctrl_read_word_sweep_derr	22.890s	48.387us	5	5	100.00
	flash_ctrl_ro_derr	150.810s	769.938us	10	10	100.00
	flash_ctrl_rw_derr	1625.440s	200000.000us	8	10	80.00
	flash_ctrl_derr_detect	207.840s	17900.405us	5	5	100.00
	flash_ctrl_integrity	439.150s	9244.764us	3	5	60.00
single_bit_err				25	25	100.00
	flash_ctrl_read_word_sweep_serr	22.510s	37.719us	5	5	100.00
	flash_ctrl_ro_serr	110.910s	594.113us	10	10	100.00
	flash_ctrl_rw_serr	237.140s	9105.428us	10	10	100.00
singlebit_err_counter				5	5	100.00
	flash_ctrl_serr_counter	61.810s	920.398us	5	5	100.00
singlebit_err_address				5	5	100.00
	flash_ctrl_serr_address	83.620s	1791.692us	5	5	100.00
scramble				56	62	90.32
	flash_ctrl_wo	2559.900s	200000.000us	19	20	95.00
	flash_ctrl_write_word_sweep	9.450s	56.774us	1	1	100.00
	flash_ctrl_read_word_sweep	11.710s	132.766us	1	1	100.00
	flash_ctrl_ro	112.590s	1158.456us	18	20	90.00
	flash_ctrl_rw	528.440s	49572.174us	17	20	85.00
filesystem_support				5	5	100.00
	flash_ctrl_fs_sup	37.130s	706.520us	5	5	100.00
rma_write_process_error				23	23	100.00
	flash_ctrl_rma_err	767.480s	70109.212us	3	3	100.00
	flash_ctrl_hw_prog_rma_wipe_err	283.740s	10019.828us	20	20	100.00
alert_test				50	50	100.00
	flash_ctrl_alert_test	14.610s	602.483us	50	50	100.00
intr_test				50	50	100.00
	flash_ctrl_intr_test	13.420s	20.141us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	flash_ctrl_tl_errors	19.060s	86.581us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	flash_ctrl_tl_errors	19.060s	86.581us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	flash_ctrl_csr_hw_reset	33.130s	26.323us	5	5	100.00
	flash_ctrl_csr_rw	18.780s	26.854us	20	20	100.00
	flash_ctrl_csr_aliasing	47.340s	460.578us	5	5	100.00
	flash_ctrl_same_csr_outstanding	22.220s	433.638us	20	20	100.00
tl_d_partial_access				50	50	100.00
	flash_ctrl_csr_hw_reset	33.130s	26.323us	5	5	100.00
	flash_ctrl_csr_rw	18.780s	26.854us	20	20	100.00
	flash_ctrl_csr_aliasing	47.340s	460.578us	5	5	100.00
	flash_ctrl_same_csr_outstanding	22.220s	433.638us	20	20	100.00

V2S

475/485 passed

97.94 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
shadow_reg_update_error				20	20	100.00
	flash_ctrl_shadow_reg_errors	54.540s	48.331us	20	20	100.00
shadow_reg_read_clear_staged_value				20	20	100.00
	flash_ctrl_shadow_reg_errors	54.540s	48.331us	20	20	100.00
shadow_reg_storage_error				20	20	100.00
	flash_ctrl_shadow_reg_errors	54.540s	48.331us	20	20	100.00
shadowed_reset_glitch				20	20	100.00
	flash_ctrl_shadow_reg_errors	54.540s	48.331us	20	20	100.00
shadow_reg_update_error_with_csr_rw				20	20	100.00
	flash_ctrl_shadow_reg_errors_with_csr_rw	88.640s	312.230us	20	20	100.00
tl_intg_err				25	25	100.00
	flash_ctrl_tl_intg_err	563.490s	2655.442us	20	20	100.00
	flash_ctrl_sec_cm	2070.110s	2898.984us	5	5	100.00
sec_cm_reg_bus_integrity				20	20	100.00
	flash_ctrl_tl_intg_err	563.490s	2655.442us	20	20	100.00
sec_cm_host_bus_integrity				20	20	100.00
	flash_ctrl_tl_intg_err	563.490s	2655.442us	20	20	100.00
sec_cm_mem_bus_integrity				6	6	100.00
	flash_ctrl_rd_intg	28.190s	216.730us	3	3	100.00
	flash_ctrl_wr_intg	12.240s	49.994us	3	3	100.00
sec_cm_scramble_key_sideload				50	50	100.00
	flash_ctrl_smoke	144.840s	126.326us	50	50	100.00
sec_cm_lc_ctrl_intersig_mubi				258	260	99.23
	flash_ctrl_otp_reset	131.670s	131.052us	78	80	97.50
	flash_ctrl_disable	23.090s	59.384us	50	50	100.00
	flash_ctrl_sec_info_access	96.800s	37674.834us	50	50	100.00
	flash_ctrl_connect	17.010s	16.250us	80	80	100.00
sec_cm_ctrl_config_regwen				5	5	100.00
	flash_ctrl_config_regwen	12.630s	26.857us	5	5	100.00
sec_cm_data_regions_config_regwen				20	20	100.00
	flash_ctrl_csr_rw	18.780s	26.854us	20	20	100.00
sec_cm_data_regions_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	54.540s	48.331us	20	20	100.00
sec_cm_info_regions_config_regwen				20	20	100.00
	flash_ctrl_csr_rw	18.780s	26.854us	20	20	100.00
sec_cm_info_regions_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	54.540s	48.331us	20	20	100.00
sec_cm_bank_config_regwen				20	20	100.00
	flash_ctrl_csr_rw	18.780s	26.854us	20	20	100.00
sec_cm_bank_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	54.540s	48.331us	20	20	100.00
sec_cm_mem_ctrl_global_esc				50	50	100.00
	flash_ctrl_disable	23.090s	59.384us	50	50	100.00
sec_cm_mem_ctrl_local_esc				6	6	100.00
	flash_ctrl_rd_intg	28.190s	216.730us	3	3	100.00
	flash_ctrl_access_after_disable	12.020s	71.029us	3	3	100.00
sec_cm_mem_addr_infection				3	3	100.00
	flash_ctrl_host_addr_infection	30.320s	28.692us	3	3	100.00
sec_cm_mem_disable_config_mubi				50	50	100.00
	flash_ctrl_disable	23.090s	59.384us	50	50	100.00
sec_cm_exec_config_redun				10	10	100.00
	flash_ctrl_fetch_code	28.380s	498.268us	10	10	100.00
sec_cm_mem_scramble				17	20	85.00
	flash_ctrl_rw	528.440s	49572.174us	17	20	85.00
sec_cm_mem_integrity				21	25	84.00
	flash_ctrl_rw_serr	237.140s	9105.428us	10	10	100.00
	flash_ctrl_rw_derr	1625.440s	200000.000us	8	10	80.00
	flash_ctrl_integrity	439.150s	9244.764us	3	5	60.00
sec_cm_rma_entry_mem_sec_wipe				3	3	100.00
	flash_ctrl_hw_rma	1572.130s	170390.239us	3	3	100.00
sec_cm_ctrl_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2070.110s	2898.984us	5	5	100.00
sec_cm_phy_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2070.110s	2898.984us	5	5	100.00
sec_cm_phy_prog_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2070.110s	2898.984us	5	5	100.00
sec_cm_ctr_redun				5	5	100.00
	flash_ctrl_sec_cm	2070.110s	2898.984us	5	5	100.00
sec_cm_phy_arbiter_ctrl_redun				5	5	100.00
	flash_ctrl_phy_arb_redun	26.200s	763.419us	5	5	100.00
sec_cm_phy_host_grant_ctrl_consistency				4	5	80.00
	flash_ctrl_phy_host_grant_err	11.660s	23.291us	4	5	80.00
sec_cm_phy_ack_ctrl_consistency				5	5	100.00
	flash_ctrl_phy_ack_consistency	17.220s	70.481us	5	5	100.00
sec_cm_fifo_ctr_redun				5	5	100.00
	flash_ctrl_sec_cm	2070.110s	2898.984us	5	5	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2070.110s	2898.984us	5	5	100.00
sec_cm_prog_tl_lc_gate_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2070.110s	2898.984us	5	5	100.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
asymmetric_read_path				1	1	100.00
	flash_ctrl_rd_ooo	20.870s	43.495us	1	1	100.00

unmapped

3/3 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				3	3	100.00
	flash_ctrl_basic_rw	612.640s	2981.359us	3	3	100.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ns hit, indicating a probable testbench issue
	flash_ctrl_wo	50931480717969899106576450588383940101619981816503254915459407737117525012311	108	UVM_FATAL @ 200000000.0 ns: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000.0 ns hit, indicating a probable testbench issue UVM_INFO @ 200000000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_rw_derr	102299254812862242008795046430535761735874745797332628811555426821710280514373	108	UVM_FATAL @ 200000000.0 ns: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000.0 ns hit, indicating a probable testbench issue UVM_INFO @ 200000000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))'
	flash_ctrl_phy_host_grant_err	28553970881007532043696946127347327397644890615646460349428803001063781386972	125	Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))' UVM_ERROR @ 4852.3 ns: (alert_esc_if.sv:201) [ASSERT FAILED] AlertKnown_A UVM_INFO @ 4852.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:267) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [] vs [*]) alert recov_err triggered unexpectedly
	flash_ctrl_ro	60436022443840124479095648467393924432291961794053602989885739530057525760772	108	UVM_ERROR @ 1289072.8 ns: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly UVM_INFO @ 1289072.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_ro	48781487592717861997331108023636680748877123971969316649297729664985943591932	108	UVM_ERROR @ 6150.3 ns: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly UVM_INFO @ 6150.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes
	flash_ctrl_rw	71795023281087984379437349009538837182361238624613991324658665626584005708857	None	Job timed out after 60 minutes
	flash_ctrl_rw_derr	85172263058786253897488928299454665657070555886560375028418287388206587477955	None	Job timed out after 60 minutes
	flash_ctrl_integrity	73942182347478377344009077578384083869734963492925335339647649033437981963714	None	Job timed out after 60 minutes
	flash_ctrl_intr_wr_slow_flash	105475719138902284408025345524096160334722054150518154393634114160092944754059	None	Job timed out after 60 minutes
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:290) m_otf_scb [process_read] unexpected double bit error *
	flash_ctrl_integrity	35144861432594816546595914919795715606188470193450655945524503056992196524478	108	UVM_ERROR @ 5826944.0 ns: (flash_ctrl_otf_scoreboard.sv:290) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00080000 UVM_INFO @ 5826944.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: flash_ctrl_core_reg_block.op_status.err reset value:
	flash_ctrl_rw_evict	28318892123784140751930382454021760291182985662579981829573321238953024789086	108	UVM_ERROR @ 77800.0 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0 UVM_INFO @ 77800.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_rw_evict_all_en	5173931375838783847760607522616483984062078720652375301205873263887172922025	108	UVM_ERROR @ 47325.2 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0 UVM_INFO @ 47325.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_rw_evict_all_en	54373940200897747588932598715637779196845437280192143070652585478147104054454	108	UVM_ERROR @ 51104.2 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0 UVM_INFO @ 51104.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:267) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [] vs [*]) alert fatal_err triggered unexpectedly
	flash_ctrl_rw	106295074107227545337660021213515586050021433589553482233568174308753024089441	108	UVM_ERROR @ 1457990.0 ns: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly UVM_INFO @ 1457990.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_rw	51008785140510760953959293996884212944221329822031106407177347548634524697115	108	UVM_ERROR @ 2121090.2 ns: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly UVM_INFO @ 2121090.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending 'dst_req_o'
	flash_ctrl_otp_reset	108775640867196590193250985681043619462902186894904481565899931045143564146923	185	Offending 'dst_req_o' UVM_ERROR @ 34032.1 ns: (prim_sync_reqack.sv:354) [ASSERT FAILED] SyncReqAckAckNeedsReq UVM_INFO @ 34032.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_otp_reset	102451006353477709709349243031758245847274370372591992942095430594456131770675	213	Offending 'dst_req_o' UVM_ERROR @ 91568.1 ns: (prim_sync_reqack.sv:354) [ASSERT FAILED] SyncReqAckAckNeedsReq UVM_INFO @ 91568.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] : obs:exp cff422_6b06df92:ffffffff_6b06df* mismatch!!
	flash_ctrl_intr_rd	35876877762810267441542118433574545873610543164970606002632018802929738716779	108	UVM_ERROR @ 2792864.5 ns: (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] 4: obs:exp 41cff422_6b06df92:ffffffff_6b06df92 mismatch!! UVM_INFO @ 2792864.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---