Simulation Results: hmac

 
25/04/2026 09:02:00 DVSim: v1.17.3 sha: 8007f61 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 99.05 %
  • code
  • 99.34 %
  • assert
  • 97.80 %
  • func
  • 100.00 %
  • line
  • 99.90 %
  • branch
  • 99.83 %
  • cond
  • 96.96 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 21.510s 2141.304us 10 10 100.00
csr_hw_reset 5 5 100.00
hmac_csr_hw_reset 1.370s 65.504us 5 5 100.00
csr_rw 20 20 100.00
hmac_csr_rw 1.290s 51.873us 20 20 100.00
csr_bit_bash 5 5 100.00
hmac_csr_bit_bash 12.550s 1220.423us 5 5 100.00
csr_aliasing 5 5 100.00
hmac_csr_aliasing 6.800s 932.453us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
hmac_csr_mem_rw_with_rand_reset 968.880s 120702.333us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
hmac_csr_rw 1.290s 51.873us 20 20 100.00
hmac_csr_aliasing 6.800s 932.453us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 99.260s 26280.728us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 100.760s 7058.812us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 287.980s 14288.900us 30 30 100.00
hmac_test_sha384_vectors 546.850s 57953.442us 75 75 100.00
hmac_test_sha512_vectors 526.130s 56790.255us 75 75 100.00
hmac_test_hmac256_vectors 14.860s 1189.557us 50 50 100.00
hmac_test_hmac384_vectors 17.540s 758.518us 60 60 100.00
hmac_test_hmac512_vectors 19.830s 2362.251us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 43.830s 3212.424us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 1487.080s 7544.727us 10 10 100.00
error 10 10 100.00
hmac_error 98.980s 29167.735us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 118.860s 32715.251us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 21.510s 2141.304us 10 10 100.00
hmac_long_msg 99.260s 26280.728us 10 10 100.00
hmac_back_pressure 100.760s 7058.812us 25 25 100.00
hmac_datapath_stress 1487.080s 7544.727us 10 10 100.00
hmac_burst_wr 43.830s 3212.424us 50 50 100.00
hmac_stress_all 1866.050s 77212.961us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 21.510s 2141.304us 10 10 100.00
hmac_long_msg 99.260s 26280.728us 10 10 100.00
hmac_back_pressure 100.760s 7058.812us 25 25 100.00
hmac_datapath_stress 1487.080s 7544.727us 10 10 100.00
hmac_wipe_secret 118.860s 32715.251us 10 10 100.00
hmac_test_sha256_vectors 287.980s 14288.900us 30 30 100.00
hmac_test_sha384_vectors 546.850s 57953.442us 75 75 100.00
hmac_test_sha512_vectors 526.130s 56790.255us 75 75 100.00
hmac_test_hmac256_vectors 14.860s 1189.557us 50 50 100.00
hmac_test_hmac384_vectors 17.540s 758.518us 60 60 100.00
hmac_test_hmac512_vectors 19.830s 2362.251us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 21.510s 2141.304us 10 10 100.00
hmac_long_msg 99.260s 26280.728us 10 10 100.00
hmac_back_pressure 100.760s 7058.812us 25 25 100.00
hmac_datapath_stress 1487.080s 7544.727us 10 10 100.00
hmac_burst_wr 43.830s 3212.424us 50 50 100.00
hmac_error 98.980s 29167.735us 10 10 100.00
hmac_wipe_secret 118.860s 32715.251us 10 10 100.00
hmac_test_sha256_vectors 287.980s 14288.900us 30 30 100.00
hmac_test_sha384_vectors 546.850s 57953.442us 75 75 100.00
hmac_test_sha512_vectors 526.130s 56790.255us 75 75 100.00
hmac_test_hmac256_vectors 14.860s 1189.557us 50 50 100.00
hmac_test_hmac384_vectors 17.540s 758.518us 60 60 100.00
hmac_test_hmac512_vectors 19.830s 2362.251us 75 75 100.00
hmac_stress_all 1866.050s 77212.961us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 1866.050s 77212.961us 50 50 100.00
alert_test 50 50 100.00
hmac_alert_test 0.940s 26.148us 50 50 100.00
intr_test 50 50 100.00
hmac_intr_test 0.970s 15.508us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
hmac_tl_errors 4.670s 329.613us 20 20 100.00
tl_d_illegal_access 20 20 100.00
hmac_tl_errors 4.670s 329.613us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
hmac_csr_hw_reset 1.370s 65.504us 5 5 100.00
hmac_csr_rw 1.290s 51.873us 20 20 100.00
hmac_csr_aliasing 6.800s 932.453us 5 5 100.00
hmac_same_csr_outstanding 3.000s 255.323us 20 20 100.00
tl_d_partial_access 50 50 100.00
hmac_csr_hw_reset 1.370s 65.504us 5 5 100.00
hmac_csr_rw 1.290s 51.873us 20 20 100.00
hmac_csr_aliasing 6.800s 932.453us 5 5 100.00
hmac_same_csr_outstanding 3.000s 255.323us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
hmac_tl_intg_err 5.570s 3569.346us 20 20 100.00
hmac_sec_cm 1.500s 89.488us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
hmac_tl_intg_err 5.570s 3569.346us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 21.510s 2141.304us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 8.870s 558.766us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 1230.680s 489456.151us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.020s 314.615us 1 1 100.00