Simulation Results: kmac/masked

 
25/04/2026 09:02:00 DVSim: v1.17.3 sha: 8007f61 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.74 %
  • code
  • 94.25 %
  • assert
  • 97.98 %
  • func
  • 97.99 %
  • line
  • 99.25 %
  • branch
  • 97.08 %
  • cond
  • 94.76 %
  • toggle
  • 99.89 %
  • FSM
  • 80.28 %
Validation stages
V1
100.00%
V2
99.48%
V2S
100.00%
V3
70.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
kmac_smoke 85.050s 13596.295us 50 50 100.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 1.400s 26.528us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.610s 125.441us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 14.480s 1463.440us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 7.070s 409.164us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 2.810s 78.072us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.610s 125.441us 20 20 100.00
kmac_csr_aliasing 7.070s 409.164us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 1.120s 20.886us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.940s 96.658us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 3295.570s 332746.949us 50 50 100.00
burst_write 50 50 100.00
kmac_burst_write 1300.130s 131774.016us 50 50 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 2131.030s 63440.082us 5 5 100.00
kmac_test_vectors_sha3_256 2277.730s 180496.460us 5 5 100.00
kmac_test_vectors_sha3_384 1513.550s 278409.019us 5 5 100.00
kmac_test_vectors_sha3_512 1054.970s 67619.362us 5 5 100.00
kmac_test_vectors_shake_128 1817.290s 43015.548us 5 5 100.00
kmac_test_vectors_shake_256 2255.630s 483010.987us 5 5 100.00
kmac_test_vectors_kmac 3.590s 177.380us 5 5 100.00
kmac_test_vectors_kmac_xof 3.310s 50.930us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 479.330s 18375.870us 50 50 100.00
app 50 50 100.00
kmac_app 355.720s 38417.913us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 368.940s 235109.051us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 433.540s 16593.849us 50 50 100.00
error 47 50 94.00
kmac_error 423.280s 12654.411us 47 50 94.00
key_error 50 50 100.00
kmac_key_error 18.370s 16232.154us 50 50 100.00
sideload_invalid 50 50 100.00
kmac_sideload_invalid 11.360s 4399.795us 50 50 100.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 46.550s 7505.341us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 9.760s 1397.051us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 69.850s 15307.633us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 46.710s 1454.053us 50 50 100.00
stress_all 49 50 98.00
kmac_stress_all 3389.840s 503226.195us 49 50 98.00
intr_test 50 50 100.00
kmac_intr_test 1.180s 14.229us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.370s 47.087us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 3.290s 98.845us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 3.290s 98.845us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 1.400s 26.528us 5 5 100.00
kmac_csr_rw 1.610s 125.441us 20 20 100.00
kmac_csr_aliasing 7.070s 409.164us 5 5 100.00
kmac_same_csr_outstanding 2.410s 61.014us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 1.400s 26.528us 5 5 100.00
kmac_csr_rw 1.610s 125.441us 20 20 100.00
kmac_csr_aliasing 7.070s 409.164us 5 5 100.00
kmac_same_csr_outstanding 2.410s 61.014us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.150s 129.595us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.150s 129.595us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.150s 129.595us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.150s 129.595us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
kmac_shadow_reg_errors_with_csr_rw 5.280s 452.396us 20 20 100.00
tl_intg_err 25 25 100.00
kmac_tl_intg_err 4.080s 191.087us 20 20 100.00
kmac_sec_cm 95.530s 12840.234us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 4.080s 191.087us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 46.710s 1454.053us 50 50 100.00
sec_cm_sw_key_key_masking 50 50 100.00
kmac_smoke 85.050s 13596.295us 50 50 100.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 479.330s 18375.870us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.150s 129.595us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 95.530s 12840.234us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 95.530s 12840.234us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 95.530s 12840.234us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 50 50 100.00
kmac_smoke 85.050s 13596.295us 50 50 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 46.710s 1454.053us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 95.530s 12840.234us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 353.680s 14248.753us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 50 50 100.00
kmac_smoke 85.050s 13596.295us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 7 10 70.00
kmac_stress_all_with_rand_reset 359.220s 4118.098us 7 10 70.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:847) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*])
kmac_stress_all_with_rand_reset 62085539012737392141503012633827882852618564014721961261686483797257028057440 317
UVM_ERROR @ 1796522902 ps: (cip_base_vseq.sv:847) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 1796522902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 48342743908660263435250986209728042896140012728493812434329250840925891710343 436
UVM_ERROR @ 4495586116 ps: (cip_base_vseq.sv:847) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 4495586116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 37241983253317928049178643136581154666898483410654731077818750290626123598755 250
UVM_ERROR @ 6500459668 ps: (cip_base_vseq.sv:847) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 6500459668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
kmac_error 100259994084917818579311102038031779851059997138269049855625229636450338496969 220
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_error 67034702472903760962514927387616382915063146712419976206212282638814201626342 236
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_error 96044007545351597927760395418163675037680871837039370535017453123541427246200 210
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: *
kmac_stress_all 77159034371329344113141351987545179517821849742126694055718505320584018606128 230
UVM_ERROR @ 65279582095 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 65279582095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---