Simulation Results: lc_ctrl/volatile_unlock_enabled

 
25/04/2026 09:02:00 DVSim: v1.17.3 sha: 8007f61 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.26 %
  • code
  • 86.40 %
  • assert
  • 94.13 %
  • func
  • 96.26 %
  • line
  • 97.24 %
  • branch
  • 94.36 %
  • cond
  • 81.70 %
  • toggle
  • 89.54 %
  • FSM
  • 69.16 %
Validation stages
V1
100.00%
V2
98.90%
V2S
100.00%
V3
58.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
lc_ctrl_smoke 6.190s 1129.571us 50 50 100.00
csr_hw_reset 5 5 100.00
lc_ctrl_csr_hw_reset 1.630s 22.012us 5 5 100.00
csr_rw 20 20 100.00
lc_ctrl_csr_rw 1.480s 20.321us 20 20 100.00
csr_bit_bash 5 5 100.00
lc_ctrl_csr_bit_bash 1.870s 654.523us 5 5 100.00
csr_aliasing 5 5 100.00
lc_ctrl_csr_aliasing 1.680s 119.747us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.900s 295.084us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
lc_ctrl_csr_rw 1.480s 20.321us 20 20 100.00
lc_ctrl_csr_aliasing 1.680s 119.747us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 50 50 100.00
lc_ctrl_state_post_trans 9.630s 345.284us 50 50 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 17.790s 294.891us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.310s 13.705us 10 10 100.00
lc_prog_failure 50 50 100.00
lc_ctrl_prog_failure 4.540s 160.661us 50 50 100.00
lc_state_failure 50 50 100.00
lc_ctrl_state_failure 14.780s 338.722us 50 50 100.00
lc_errors 46 50 92.00
lc_ctrl_errors 19.840s 790.421us 46 50 92.00
security_escalation 253 260 97.31
lc_ctrl_state_failure 14.780s 338.722us 50 50 100.00
lc_ctrl_prog_failure 4.540s 160.661us 50 50 100.00
lc_ctrl_errors 19.840s 790.421us 46 50 92.00
lc_ctrl_security_escalation 11.880s 824.297us 50 50 100.00
lc_ctrl_jtag_state_failure 58.680s 2412.174us 20 20 100.00
lc_ctrl_jtag_prog_failure 16.920s 764.975us 20 20 100.00
lc_ctrl_jtag_errors 78.680s 7898.789us 17 20 85.00
jtag_access 207 210 98.57
lc_ctrl_jtag_smoke 11.060s 924.945us 20 20 100.00
lc_ctrl_jtag_state_post_trans 23.310s 2883.802us 20 20 100.00
lc_ctrl_jtag_prog_failure 16.920s 764.975us 20 20 100.00
lc_ctrl_jtag_errors 78.680s 7898.789us 17 20 85.00
lc_ctrl_jtag_access 20.780s 3605.625us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 27.930s 1012.947us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 3.920s 347.592us 10 10 100.00
lc_ctrl_jtag_csr_rw 2.340s 246.181us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 30.070s 1849.253us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 9.630s 1831.818us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 2.430s 43.399us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 5.770s 766.529us 10 10 100.00
lc_ctrl_jtag_alert_test 2.520s 183.105us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 33.450s 1672.420us 10 10 100.00
lc_ctrl_volatile_unlock 50 50 100.00
lc_ctrl_volatile_unlock_smoke 1.580s 25.860us 50 50 100.00
stress_all 49 50 98.00
lc_ctrl_stress_all 838.830s 29337.557us 49 50 98.00
alert_test 50 50 100.00
lc_ctrl_alert_test 1.720s 124.069us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
lc_ctrl_tl_errors 3.620s 122.786us 20 20 100.00
tl_d_illegal_access 20 20 100.00
lc_ctrl_tl_errors 3.620s 122.786us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.630s 22.012us 5 5 100.00
lc_ctrl_csr_rw 1.480s 20.321us 20 20 100.00
lc_ctrl_csr_aliasing 1.680s 119.747us 5 5 100.00
lc_ctrl_same_csr_outstanding 1.800s 189.209us 20 20 100.00
tl_d_partial_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.630s 22.012us 5 5 100.00
lc_ctrl_csr_rw 1.480s 20.321us 20 20 100.00
lc_ctrl_csr_aliasing 1.680s 119.747us 5 5 100.00
lc_ctrl_same_csr_outstanding 1.800s 189.209us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
lc_ctrl_sec_cm 10.140s 588.658us 5 5 100.00
lc_ctrl_tl_intg_err 3.510s 85.972us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
lc_ctrl_tl_intg_err 3.510s 85.972us 20 20 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 17.790s 294.891us 10 10 100.00
sec_cm_manuf_state_sparse 55 55 100.00
lc_ctrl_state_failure 14.780s 338.722us 50 50 100.00
lc_ctrl_sec_cm 10.140s 588.658us 5 5 100.00
sec_cm_transition_ctr_sparse 55 55 100.00
lc_ctrl_state_failure 14.780s 338.722us 50 50 100.00
lc_ctrl_sec_cm 10.140s 588.658us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 14.780s 338.722us 50 50 100.00
lc_ctrl_sec_cm 10.140s 588.658us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 14.780s 338.722us 50 50 100.00
lc_ctrl_sec_cm 10.140s 588.658us 5 5 100.00
sec_cm_state_config_sparse 55 55 100.00
lc_ctrl_state_failure 14.780s 338.722us 50 50 100.00
lc_ctrl_sec_cm 10.140s 588.658us 5 5 100.00
sec_cm_main_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 14.780s 338.722us 50 50 100.00
lc_ctrl_sec_cm 10.140s 588.658us 5 5 100.00
sec_cm_kmac_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 14.780s 338.722us 50 50 100.00
lc_ctrl_sec_cm 10.140s 588.658us 5 5 100.00
sec_cm_main_fsm_local_esc 55 55 100.00
lc_ctrl_state_failure 14.780s 338.722us 50 50 100.00
lc_ctrl_sec_cm 10.140s 588.658us 5 5 100.00
sec_cm_main_fsm_global_esc 50 50 100.00
lc_ctrl_security_escalation 11.880s 824.297us 50 50 100.00
sec_cm_main_ctrl_flow_consistency 70 70 100.00
lc_ctrl_state_post_trans 9.630s 345.284us 50 50 100.00
lc_ctrl_jtag_state_post_trans 23.310s 2883.802us 20 20 100.00
sec_cm_intersig_mubi 50 50 100.00
lc_ctrl_sec_mubi 16.060s 8926.751us 50 50 100.00
sec_cm_token_valid_ctrl_mubi 50 50 100.00
lc_ctrl_sec_mubi 16.060s 8926.751us 50 50 100.00
sec_cm_token_digest 50 50 100.00
lc_ctrl_sec_token_digest 18.740s 701.780us 50 50 100.00
sec_cm_token_mux_ctrl_redun 50 50 100.00
lc_ctrl_sec_token_mux 16.320s 537.105us 50 50 100.00
sec_cm_token_valid_mux_redun 50 50 100.00
lc_ctrl_sec_token_mux 16.320s 537.105us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 29 50 58.00
lc_ctrl_stress_all_with_rand_reset 151.860s 6142.545us 29 50 58.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 28369130242487341564951284771736292251468862512943362066035397746500582757454 203
UVM_ERROR @ 6399797407 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 6399797407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 33329293839387736535014009329879389722843285995170053640524770747078758139703 152
UVM_ERROR @ 540188875 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 540188875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 89241977248255902760661876140699272757304050202349945025507517200557011872617 4641
UVM_ERROR @ 4845843077 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4845843077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 22618705376671930100389963672545417974773667054397282490107285876478189389533 7781
UVM_ERROR @ 37936130199 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 37936130199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 37375726314274226666651588851295244627882865418600948615495705723628258501590 4354
UVM_ERROR @ 9558043773 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 9558043773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 33178076966251033888894533819984763039955244543415954985178944948742402643987 158
UVM_ERROR @ 11800191050 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 11800191050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 6996838602255058265863187354152022273155476196197272011033061831564390517228 4669
UVM_ERROR @ 2031602318 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2031602318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 32322931499103338294722063467640504981344528864306384327551456764328863247049 151
UVM_ERROR @ 419214350 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 419214350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 85269271969941591780647302064606193659720418183473510479077571662843077563790 1286
UVM_ERROR @ 1704744078 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1704744078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 76849999968937374163651783572388029482020870534828791783488311919876679950395 964
UVM_ERROR @ 3575178227 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3575178227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 30373027292707799139991355361301093665982747035290266790014151092080073818785 1158
UVM_ERROR @ 20354232748 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 20354232748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 83385310304375162765506279690934541341211994607755547095844012616768775657209 152
UVM_ERROR @ 1433088571 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1433088571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 27385546407694523240873655767566827171724447119967661324153642355289538613338 8952
UVM_ERROR @ 4451501918 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4451501918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 26722462174191488011757493447950186535457383327494510127162963192491527948238 4981
UVM_ERROR @ 1624244735 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1624244735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 85289067053202194890698839329664944317654274104096552918957656838070759046283 13634
UVM_ERROR @ 13968397906 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 13968397906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 46066231359550986641953609881857929063204658571756439801073949850570126261893 156
UVM_ERROR @ 1267519264 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1267519264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*])
lc_ctrl_jtag_errors 46967278087323020992818157134263196263040084976587977141774631508471324297036 380
UVM_ERROR @ 107422665 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 107422665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 33180832084386692519383437857757908191903350524366758089457356713526370645133 2544
UVM_ERROR @ 474524112 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 474524112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_errors 90225374916748151178379166393755867855864549654121790733418379568510458965530 3046
UVM_ERROR @ 12136629810 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 12136629810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_errors 49521422790598197643107901435911774178728499843269690780453779038198683966734 1299
UVM_ERROR @ 3672699284 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 3672699284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 25631094457470895829544378599484770233859910548949150469486604990026970297922 3129
UVM_ERROR @ 298126946 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 298126946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 10037150230936420372857958901709439787394153866412150528012068000156383887311 123
UVM_ERROR @ 17981731 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 17981731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 112625064663728643722470396269891500495533194236119959239096669116803596523451 1632
UVM_ERROR @ 140934142 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 140934142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 105336923348343086914672640282848926650893804502172110964127533915194068507226 6272
UVM_ERROR @ 1691430056 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1691430056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 1767113243759884324211232159363987194801593684247931700867870731864787407457 2101
UVM_ERROR @ 592359188 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 592359188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 785208789770660068371864647129481705065079077275538495002859955149472641678 8152
UVM_ERROR @ 1888633340 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1888633340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 114934419236359173542009733301886332929670277347437559432474929938491970019870 6340
UVM_ERROR @ 5925685738 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 5925685738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
lc_ctrl_stress_all_with_rand_reset 88622280486004381623701555682556506723473765489019942623007477051779009602412 10114
UVM_ERROR @ 2669465762 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
UVM_INFO @ 2669465762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 66037154513912608326547919569753481220922981890010513610273402311540389386889 3376
UVM_ERROR @ 997523259 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
UVM_INFO @ 997523259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---