| V1 |
|
99.40% |
| V2 |
|
97.83% |
| V2S |
|
95.87% |
| V3 |
|
40.00% |
| unmapped |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| otbn_smoke | 9.000s | 41.487us | 1 | 1 | 100.00 | |
| single_binary | 99 | 100 | 99.00 | |||
| otbn_single | 200.000s | 727.615us | 99 | 100 | 99.00 | |
| csr_hw_reset | 5 | 5 | 100.00 | |||
| otbn_csr_hw_reset | 7.000s | 23.498us | 5 | 5 | 100.00 | |
| csr_rw | 20 | 20 | 100.00 | |||
| otbn_csr_rw | 5.000s | 39.221us | 20 | 20 | 100.00 | |
| csr_bit_bash | 5 | 5 | 100.00 | |||
| otbn_csr_bit_bash | 10.000s | 357.977us | 5 | 5 | 100.00 | |
| csr_aliasing | 5 | 5 | 100.00 | |||
| otbn_csr_aliasing | 6.000s | 26.513us | 5 | 5 | 100.00 | |
| csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 | |||
| otbn_csr_mem_rw_with_rand_reset | 8.000s | 43.318us | 20 | 20 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 25 | 25 | 100.00 | |||
| otbn_csr_rw | 5.000s | 39.221us | 20 | 20 | 100.00 | |
| otbn_csr_aliasing | 6.000s | 26.513us | 5 | 5 | 100.00 | |
| mem_walk | 5 | 5 | 100.00 | |||
| otbn_mem_walk | 100.000s | 4135.992us | 5 | 5 | 100.00 | |
| mem_partial_access | 5 | 5 | 100.00 | |||
| otbn_mem_partial_access | 49.000s | 4375.110us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| reset_recovery | 10 | 10 | 100.00 | |||
| otbn_reset | 55.000s | 146.387us | 10 | 10 | 100.00 | |
| multi_error | 1 | 1 | 100.00 | |||
| otbn_multi_err | 57.000s | 174.328us | 1 | 1 | 100.00 | |
| back_to_back | 10 | 10 | 100.00 | |||
| otbn_multi | 74.000s | 350.589us | 10 | 10 | 100.00 | |
| stress_all | 10 | 10 | 100.00 | |||
| otbn_stress_all | 97.000s | 362.324us | 10 | 10 | 100.00 | |
| lc_escalation | 59 | 60 | 98.33 | |||
| otbn_escalate | 37.000s | 499.737us | 59 | 60 | 98.33 | |
| zero_state_err_urnd | 0 | 5 | 0.00 | |||
| otbn_zero_state_err_urnd | 5.000s | 19.240us | 0 | 5 | 0.00 | |
| sw_errs_fatal_chk | 10 | 10 | 100.00 | |||
| otbn_sw_errs_fatal_chk | 25.000s | 92.023us | 10 | 10 | 100.00 | |
| alert_test | 50 | 50 | 100.00 | |||
| otbn_alert_test | 6.000s | 23.194us | 50 | 50 | 100.00 | |
| intr_test | 50 | 50 | 100.00 | |||
| otbn_intr_test | 5.000s | 11.329us | 50 | 50 | 100.00 | |
| tl_d_oob_addr_access | 20 | 20 | 100.00 | |||
| otbn_tl_errors | 9.000s | 473.550us | 20 | 20 | 100.00 | |
| tl_d_illegal_access | 20 | 20 | 100.00 | |||
| otbn_tl_errors | 9.000s | 473.550us | 20 | 20 | 100.00 | |
| tl_d_outstanding_access | 50 | 50 | 100.00 | |||
| otbn_csr_hw_reset | 7.000s | 23.498us | 5 | 5 | 100.00 | |
| otbn_csr_rw | 5.000s | 39.221us | 20 | 20 | 100.00 | |
| otbn_csr_aliasing | 6.000s | 26.513us | 5 | 5 | 100.00 | |
| otbn_same_csr_outstanding | 7.000s | 30.557us | 20 | 20 | 100.00 | |
| tl_d_partial_access | 50 | 50 | 100.00 | |||
| otbn_csr_hw_reset | 7.000s | 23.498us | 5 | 5 | 100.00 | |
| otbn_csr_rw | 5.000s | 39.221us | 20 | 20 | 100.00 | |
| otbn_csr_aliasing | 6.000s | 26.513us | 5 | 5 | 100.00 | |
| otbn_same_csr_outstanding | 7.000s | 30.557us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| mem_integrity | 25 | 25 | 100.00 | |||
| otbn_imem_err | 12.000s | 34.679us | 10 | 10 | 100.00 | |
| otbn_dmem_err | 41.000s | 525.915us | 15 | 15 | 100.00 | |
| internal_integrity | 15 | 17 | 88.24 | |||
| otbn_alu_bignum_mod_err | 30.000s | 112.307us | 5 | 5 | 100.00 | |
| otbn_controller_ispr_rdata_err | 10.000s | 149.351us | 5 | 5 | 100.00 | |
| otbn_mac_bignum_acc_err | 9.000s | 240.244us | 5 | 5 | 100.00 | |
| otbn_urnd_err | 5.000s | 27.297us | 0 | 2 | 0.00 | |
| illegal_bus_access | 5 | 5 | 100.00 | |||
| otbn_illegal_mem_acc | 7.000s | 18.650us | 5 | 5 | 100.00 | |
| otbn_mem_gnt_acc_err | 2 | 2 | 100.00 | |||
| otbn_mem_gnt_acc_err | 6.000s | 9.832us | 2 | 2 | 100.00 | |
| otbn_non_sec_partial_wipe | 10 | 10 | 100.00 | |||
| otbn_partial_wipe | 8.000s | 114.193us | 10 | 10 | 100.00 | |
| tl_intg_err | 25 | 25 | 100.00 | |||
| otbn_tl_intg_err | 93.000s | 587.483us | 20 | 20 | 100.00 | |
| otbn_sec_cm | 244.000s | 3924.695us | 5 | 5 | 100.00 | |
| passthru_mem_tl_intg_err | 18 | 20 | 90.00 | |||
| otbn_passthru_mem_tl_intg_err | 49.000s | 215.705us | 18 | 20 | 90.00 | |
| prim_fsm_check | 5 | 5 | 100.00 | |||
| otbn_sec_cm | 244.000s | 3924.695us | 5 | 5 | 100.00 | |
| prim_count_check | 5 | 5 | 100.00 | |||
| otbn_sec_cm | 244.000s | 3924.695us | 5 | 5 | 100.00 | |
| sec_cm_mem_scramble | 1 | 1 | 100.00 | |||
| otbn_smoke | 9.000s | 41.487us | 1 | 1 | 100.00 | |
| sec_cm_data_mem_integrity | 15 | 15 | 100.00 | |||
| otbn_dmem_err | 41.000s | 525.915us | 15 | 15 | 100.00 | |
| sec_cm_instruction_mem_integrity | 10 | 10 | 100.00 | |||
| otbn_imem_err | 12.000s | 34.679us | 10 | 10 | 100.00 | |
| sec_cm_bus_integrity | 20 | 20 | 100.00 | |||
| otbn_tl_intg_err | 93.000s | 587.483us | 20 | 20 | 100.00 | |
| sec_cm_controller_fsm_global_esc | 59 | 60 | 98.33 | |||
| otbn_escalate | 37.000s | 499.737us | 59 | 60 | 98.33 | |
| sec_cm_controller_fsm_local_esc | 35 | 40 | 87.50 | |||
| otbn_imem_err | 12.000s | 34.679us | 10 | 10 | 100.00 | |
| otbn_dmem_err | 41.000s | 525.915us | 15 | 15 | 100.00 | |
| otbn_zero_state_err_urnd | 5.000s | 19.240us | 0 | 5 | 0.00 | |
| otbn_illegal_mem_acc | 7.000s | 18.650us | 5 | 5 | 100.00 | |
| otbn_sec_cm | 244.000s | 3924.695us | 5 | 5 | 100.00 | |
| sec_cm_controller_fsm_sparse | 5 | 5 | 100.00 | |||
| otbn_sec_cm | 244.000s | 3924.695us | 5 | 5 | 100.00 | |
| sec_cm_scramble_key_sideload | 99 | 100 | 99.00 | |||
| otbn_single | 200.000s | 727.615us | 99 | 100 | 99.00 | |
| sec_cm_scramble_ctrl_fsm_local_esc | 35 | 40 | 87.50 | |||
| otbn_imem_err | 12.000s | 34.679us | 10 | 10 | 100.00 | |
| otbn_dmem_err | 41.000s | 525.915us | 15 | 15 | 100.00 | |
| otbn_zero_state_err_urnd | 5.000s | 19.240us | 0 | 5 | 0.00 | |
| otbn_illegal_mem_acc | 7.000s | 18.650us | 5 | 5 | 100.00 | |
| otbn_sec_cm | 244.000s | 3924.695us | 5 | 5 | 100.00 | |
| sec_cm_scramble_ctrl_fsm_sparse | 5 | 5 | 100.00 | |||
| otbn_sec_cm | 244.000s | 3924.695us | 5 | 5 | 100.00 | |
| sec_cm_start_stop_ctrl_fsm_global_esc | 59 | 60 | 98.33 | |||
| otbn_escalate | 37.000s | 499.737us | 59 | 60 | 98.33 | |
| sec_cm_start_stop_ctrl_fsm_local_esc | 35 | 40 | 87.50 | |||
| otbn_imem_err | 12.000s | 34.679us | 10 | 10 | 100.00 | |
| otbn_dmem_err | 41.000s | 525.915us | 15 | 15 | 100.00 | |
| otbn_zero_state_err_urnd | 5.000s | 19.240us | 0 | 5 | 0.00 | |
| otbn_illegal_mem_acc | 7.000s | 18.650us | 5 | 5 | 100.00 | |
| otbn_sec_cm | 244.000s | 3924.695us | 5 | 5 | 100.00 | |
| sec_cm_start_stop_ctrl_fsm_sparse | 5 | 5 | 100.00 | |||
| otbn_sec_cm | 244.000s | 3924.695us | 5 | 5 | 100.00 | |
| sec_cm_data_reg_sw_sca | 99 | 100 | 99.00 | |||
| otbn_single | 200.000s | 727.615us | 99 | 100 | 99.00 | |
| sec_cm_ctrl_redun | 11 | 12 | 91.67 | |||
| otbn_ctrl_redun | 37.820s | 0.000us | 11 | 12 | 91.67 | |
| sec_cm_pc_ctrl_flow_redun | 5 | 5 | 100.00 | |||
| otbn_pc_ctrl_flow_redun | 9.000s | 27.460us | 5 | 5 | 100.00 | |
| sec_cm_rnd_bus_consistency | 5 | 5 | 100.00 | |||
| otbn_rnd_sec_cm | 63.000s | 220.174us | 5 | 5 | 100.00 | |
| sec_cm_rnd_rng_digest | 5 | 5 | 100.00 | |||
| otbn_rnd_sec_cm | 63.000s | 220.174us | 5 | 5 | 100.00 | |
| sec_cm_rf_base_data_reg_sw_integrity | 8 | 10 | 80.00 | |||
| otbn_rf_base_intg_err | 32.000s | 2013.331us | 8 | 10 | 80.00 | |
| sec_cm_rf_base_data_reg_sw_glitch_detect | 5 | 5 | 100.00 | |||
| otbn_sec_cm | 244.000s | 3924.695us | 5 | 5 | 100.00 | |
| sec_cm_stack_wr_ptr_ctr_redun | 5 | 5 | 100.00 | |||
| otbn_sec_cm | 244.000s | 3924.695us | 5 | 5 | 100.00 | |
| sec_cm_rf_bignum_data_reg_sw_integrity | 10 | 10 | 100.00 | |||
| otbn_rf_bignum_intg_err | 14.000s | 356.732us | 10 | 10 | 100.00 | |
| sec_cm_rf_bignum_data_reg_sw_glitch_detect | 5 | 5 | 100.00 | |||
| otbn_sec_cm | 244.000s | 3924.695us | 5 | 5 | 100.00 | |
| sec_cm_loop_stack_ctr_redun | 5 | 5 | 100.00 | |||
| otbn_sec_cm | 244.000s | 3924.695us | 5 | 5 | 100.00 | |
| sec_cm_loop_stack_addr_integrity | 5 | 5 | 100.00 | |||
| otbn_stack_addr_integ_chk | 20.000s | 37.588us | 5 | 5 | 100.00 | |
| sec_cm_call_stack_addr_integrity | 5 | 5 | 100.00 | |||
| otbn_stack_addr_integ_chk | 20.000s | 37.588us | 5 | 5 | 100.00 | |
| sec_cm_start_stop_ctrl_state_consistency | 7 | 7 | 100.00 | |||
| otbn_sec_wipe_err | 11.000s | 88.321us | 7 | 7 | 100.00 | |
| sec_cm_data_mem_sec_wipe | 99 | 100 | 99.00 | |||
| otbn_single | 200.000s | 727.615us | 99 | 100 | 99.00 | |
| sec_cm_instruction_mem_sec_wipe | 99 | 100 | 99.00 | |||
| otbn_single | 200.000s | 727.615us | 99 | 100 | 99.00 | |
| sec_cm_data_reg_sw_sec_wipe | 99 | 100 | 99.00 | |||
| otbn_single | 200.000s | 727.615us | 99 | 100 | 99.00 | |
| sec_cm_write_mem_integrity | 10 | 10 | 100.00 | |||
| otbn_multi | 74.000s | 350.589us | 10 | 10 | 100.00 | |
| sec_cm_ctrl_flow_count | 99 | 100 | 99.00 | |||
| otbn_single | 200.000s | 727.615us | 99 | 100 | 99.00 | |
| sec_cm_ctrl_flow_sca | 99 | 100 | 99.00 | |||
| otbn_single | 200.000s | 727.615us | 99 | 100 | 99.00 | |
| sec_cm_data_mem_sw_noaccess | 5 | 5 | 100.00 | |||
| otbn_sw_no_acc | 11.000s | 913.640us | 5 | 5 | 100.00 | |
| sec_cm_key_sideload | 99 | 100 | 99.00 | |||
| otbn_single | 200.000s | 727.615us | 99 | 100 | 99.00 | |
| sec_cm_tlul_fifo_ctr_redun | 5 | 5 | 100.00 | |||
| otbn_sec_cm | 244.000s | 3924.695us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 4 | 10 | 40.00 | |||
| otbn_stress_all_with_rand_reset | 599.000s | 8049.926us | 4 | 10 | 40.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 1 | 1 | 100.00 | |||
| otbn_smoke_vectorized | 6.000s | 18.798us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. | ||||
| otbn_passthru_mem_tl_intg_err | 25819174475829359339857151345709143648196574984379381869166724955905500478658 | 86 |
UVM_FATAL @ 4485129 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 4485129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. | ||||
| otbn_passthru_mem_tl_intg_err | 25176808276310602680108808487729290015533353002282877455415925859926332142557 | 106 |
UVM_FATAL @ 40292995 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 40292995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otbn_single | 104886094930276688618744378705582164871761475015071003531678768738291050441364 | 118 |
UVM_FATAL @ 25859036 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 25859036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.u_otbn_core.u_otbn_rnd.u_xoshiro256pp.xoshiro_q cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) | ||||
| otbn_zero_state_err_urnd | 65210117834651321913510547767093464425735916405411460701822816225920580909799 | 126 |
UVM_ERROR @ 19240062 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.u_otbn_core.u_otbn_rnd.u_xoshiro256pp.xoshiro_q cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_INFO @ 19240062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otbn_zero_state_err_urnd | 41833594276830288648149750140961283823251194763059745749280146486157187661402 | 113 |
UVM_ERROR @ 3647182 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.u_otbn_core.u_otbn_rnd.u_xoshiro256pp.xoshiro_q cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_INFO @ 3647182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otbn_zero_state_err_urnd | 95008280576657129511790277701772773670282866230301266931759028479888484102145 | 114 |
UVM_ERROR @ 6225088 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.u_otbn_core.u_otbn_rnd.u_xoshiro256pp.xoshiro_q cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_INFO @ 6225088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otbn_zero_state_err_urnd | 25164693021410843029572224854428651683721993298237476055705434727868959979056 | 105 |
UVM_ERROR @ 26879664 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.u_otbn_core.u_otbn_rnd.u_xoshiro256pp.xoshiro_q cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_INFO @ 26879664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otbn_zero_state_err_urnd | 11938324505289650866405116768899868465529350691098815732003757989309081997735 | 105 |
UVM_ERROR @ 4576823 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.u_otbn_core.u_otbn_rnd.u_xoshiro256pp.xoshiro_q cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_INFO @ 4576823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Job returned non-zero exit code | ||||
| otbn_ctrl_redun | 65244272021313130577325377795155606929589744422804634375355852424490092919339 | None |
/nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl:392:31: in <toplevel>
ERROR: /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl:137:45: An error occurred during the fetch of repository 'rules_python+':
Traceback (most recent call last):
File "/nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl", line 137, column 45, in _http_archive_impl
download_info = ctx.download_and_extract(
Error in download_and_extract: java.io.IOException: Error downloading [https://github.com/bazelbuild/rules_python/releases/download/1.2.0/rules_python-1.2.0.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/rules_python+/temp7537359500795259694/rules_python-1.2.0.tar.gz: GET returned 502 Bad Gateway or Proxy Error
WARNING: Target pattern parsing failed.
ERROR: Skipping '@rules_rust//rust/toolchain/channel': no such package '@@rules_python+//python': java.io.IOException: Error downloading [https://github.com/bazelbuild/rules_python/releases/download/1.2.0/rules_python-1.2.0.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/rules_python+/temp7537359500795259694/rules_python-1.2.0.tar.gz: GET returned 502 Bad Gateway or Proxy Error
ERROR: @rules_rust//rust/toolchain/channel :: Error loading option @rules_rust//rust/toolchain/channel: no such package '@@rules_python+//python': java.io.IOException: Error downloading [https://github.com/bazelbuild/rules_python/releases/download/1.2.0/rules_python-1.2.0.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/rules_python+/temp7537359500795259694/rules_python-1.2.0.tar.gz: GET returned 502 Bad Gateway or Proxy Error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 2
|
|
| UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.edn_urnd_ack cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) | ||||
| otbn_urnd_err | 113203964599149849752265136535830175182260849593010408738560443361210669237073 | 118 |
UVM_ERROR @ 15134278 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.edn_urnd_ack cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_INFO @ 15134278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otbn_urnd_err | 20531021555226206686182353297809896411658981061932058527836121883579544134924 | 116 |
UVM_ERROR @ 27296762 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.edn_urnd_ack cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_INFO @ 27296762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:1237) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | ||||
| otbn_stress_all_with_rand_reset | 103254867269165095418201714360612301642770070146104323846869312228336776241996 | 220 |
UVM_ERROR @ 4572425194 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4572425194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otbn_stress_all_with_rand_reset | 32551675876220100607017308920312906971356552888626120580237461849669258848423 | 733 |
UVM_ERROR @ 2149346328 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2149346328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otbn_stress_all_with_rand_reset | 34074262729586873371183433023585866639826435503244886563861711769342296222552 | 665 |
UVM_ERROR @ 8049925602 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 8049925602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| otbn_stress_all_with_rand_reset | 29592251869705083125500737926374873610691450503329959094874713396515583225536 | 177 |
UVM_ERROR @ 8840958141 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 8840958141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| otbn_stress_all_with_rand_reset | 35051892641299499900744089058631715261510242316893765033178815802257983281779 | 206 |
UVM_ERROR @ 272702991 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 272702991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_FATAL (csr_utils_pkg.sv:372) [csr_utils_pkg::csr_rd_sub.isolation_fork] Timeout waiting to csr_rd otbn_reg_block.status (addr=*) | ||||
| otbn_rf_base_intg_err | 7617062232752052387935342682700116041690620028600643615006413626166923461204 | 117 |
UVM_FATAL @ 2013330677 ps: (csr_utils_pkg.sv:372) [csr_utils_pkg::csr_rd_sub.isolation_fork] Timeout waiting to csr_rd otbn_reg_block.status (addr=0xb7a40018)
UVM_INFO @ 2013330677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status | ||||
| otbn_escalate | 109841561096800687365591976217707486635549340562697400498776117051411327850872 | 108 |
UVM_ERROR @ 3802102 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
UVM_INFO @ 3802102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues | ||||
| otbn_stress_all_with_rand_reset | 103769551435174770689061875741938441029279491138434310477573190964643188236805 | 232 |
UVM_ERROR @ 421976304 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_otbn_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_otbn_reg_block.sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 421976304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| otbn_rf_base_intg_err | 84814282238278357215909016997548963677064629306727374143498680958787121044301 | 123 |
UVM_ERROR @ 283534178 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_otbn_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_otbn_reg_block.sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 283534178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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