| V1 |
|
94.83% |
| V2 |
|
91.25% |
| V2S |
|
88.90% |
| V3 |
|
20.79% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| wake_up | 1 | 1 | 100.00 | |||
| otp_ctrl_wake_up | 1.930s | 93.018us | 1 | 1 | 100.00 | |
| smoke | 50 | 50 | 100.00 | |||
| otp_ctrl_smoke | 16.690s | 4761.667us | 50 | 50 | 100.00 | |
| csr_hw_reset | 5 | 5 | 100.00 | |||
| otp_ctrl_csr_hw_reset | 3.910s | 991.997us | 5 | 5 | 100.00 | |
| csr_rw | 20 | 20 | 100.00 | |||
| otp_ctrl_csr_rw | 2.640s | 131.971us | 20 | 20 | 100.00 | |
| csr_bit_bash | 5 | 5 | 100.00 | |||
| otp_ctrl_csr_bit_bash | 13.710s | 1918.639us | 5 | 5 | 100.00 | |
| csr_aliasing | 5 | 5 | 100.00 | |||
| otp_ctrl_csr_aliasing | 7.800s | 2643.768us | 5 | 5 | 100.00 | |
| csr_mem_rw_with_rand_reset | 14 | 20 | 70.00 | |||
| otp_ctrl_csr_mem_rw_with_rand_reset | 6.360s | 1631.986us | 14 | 20 | 70.00 | |
| regwen_csr_and_corresponding_lockable_csr | 25 | 25 | 100.00 | |||
| otp_ctrl_csr_rw | 2.640s | 131.971us | 20 | 20 | 100.00 | |
| otp_ctrl_csr_aliasing | 7.800s | 2643.768us | 5 | 5 | 100.00 | |
| mem_walk | 5 | 5 | 100.00 | |||
| otp_ctrl_mem_walk | 2.070s | 153.484us | 5 | 5 | 100.00 | |
| mem_partial_access | 5 | 5 | 100.00 | |||
| otp_ctrl_mem_partial_access | 2.330s | 557.479us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| dai_access_partition_walk | 1 | 1 | 100.00 | |||
| otp_ctrl_partition_walk | 22.200s | 1242.352us | 1 | 1 | 100.00 | |
| init_fail | 282 | 300 | 94.00 | |||
| otp_ctrl_init_fail | 8.050s | 1943.961us | 282 | 300 | 94.00 | |
| partition_check | 26 | 60 | 43.33 | |||
| otp_ctrl_background_chks | 40.700s | 1225.446us | 10 | 10 | 100.00 | |
| otp_ctrl_check_fail | 24.850s | 1763.523us | 16 | 50 | 32.00 | |
| regwen_during_otp_init | 50 | 50 | 100.00 | |||
| otp_ctrl_regwen | 14.100s | 1177.241us | 50 | 50 | 100.00 | |
| partition_lock | 50 | 50 | 100.00 | |||
| otp_ctrl_dai_lock | 64.930s | 11465.961us | 50 | 50 | 100.00 | |
| interface_key_check | 50 | 50 | 100.00 | |||
| otp_ctrl_parallel_key_req | 91.120s | 6790.030us | 50 | 50 | 100.00 | |
| lc_interactions | 248 | 250 | 99.20 | |||
| otp_ctrl_parallel_lc_req | 29.230s | 13533.670us | 50 | 50 | 100.00 | |
| otp_ctrl_parallel_lc_esc | 38.870s | 12903.191us | 198 | 200 | 99.00 | |
| otp_dai_errors | 48 | 50 | 96.00 | |||
| otp_ctrl_dai_errs | 80.930s | 21722.074us | 48 | 50 | 96.00 | |
| otp_macro_errors | 20 | 50 | 40.00 | |||
| otp_ctrl_macro_errs | 53.030s | 5530.986us | 20 | 50 | 40.00 | |
| test_access | 50 | 50 | 100.00 | |||
| otp_ctrl_test_access | 121.100s | 28433.504us | 50 | 50 | 100.00 | |
| stress_all | 37 | 50 | 74.00 | |||
| otp_ctrl_stress_all | 277.820s | 35231.152us | 37 | 50 | 74.00 | |
| intr_test | 50 | 50 | 100.00 | |||
| otp_ctrl_intr_test | 3.090s | 573.892us | 50 | 50 | 100.00 | |
| alert_test | 50 | 50 | 100.00 | |||
| otp_ctrl_alert_test | 3.730s | 279.710us | 50 | 50 | 100.00 | |
| tl_d_oob_addr_access | 20 | 20 | 100.00 | |||
| otp_ctrl_tl_errors | 8.220s | 1981.662us | 20 | 20 | 100.00 | |
| tl_d_illegal_access | 20 | 20 | 100.00 | |||
| otp_ctrl_tl_errors | 8.220s | 1981.662us | 20 | 20 | 100.00 | |
| tl_d_outstanding_access | 50 | 50 | 100.00 | |||
| otp_ctrl_csr_hw_reset | 3.910s | 991.997us | 5 | 5 | 100.00 | |
| otp_ctrl_csr_rw | 2.640s | 131.971us | 20 | 20 | 100.00 | |
| otp_ctrl_csr_aliasing | 7.800s | 2643.768us | 5 | 5 | 100.00 | |
| otp_ctrl_same_csr_outstanding | 6.250s | 1282.303us | 20 | 20 | 100.00 | |
| tl_d_partial_access | 50 | 50 | 100.00 | |||
| otp_ctrl_csr_hw_reset | 3.910s | 991.997us | 5 | 5 | 100.00 | |
| otp_ctrl_csr_rw | 2.640s | 131.971us | 20 | 20 | 100.00 | |
| otp_ctrl_csr_aliasing | 7.800s | 2643.768us | 5 | 5 | 100.00 | |
| otp_ctrl_same_csr_outstanding | 6.250s | 1282.303us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| sec_cm_additional_check | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 146.810s | 20507.675us | 3 | 5 | 60.00 | |
| tl_intg_err | 23 | 25 | 92.00 | |||
| otp_ctrl_tl_intg_err | 30.700s | 4705.955us | 20 | 20 | 100.00 | |
| otp_ctrl_sec_cm | 146.810s | 20507.675us | 3 | 5 | 60.00 | |
| prim_count_check | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 146.810s | 20507.675us | 3 | 5 | 60.00 | |
| prim_fsm_check | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 146.810s | 20507.675us | 3 | 5 | 60.00 | |
| sec_cm_bus_integrity | 20 | 20 | 100.00 | |||
| otp_ctrl_tl_intg_err | 30.700s | 4705.955us | 20 | 20 | 100.00 | |
| sec_cm_secret_mem_scramble | 50 | 50 | 100.00 | |||
| otp_ctrl_smoke | 16.690s | 4761.667us | 50 | 50 | 100.00 | |
| sec_cm_part_mem_digest | 50 | 50 | 100.00 | |||
| otp_ctrl_smoke | 16.690s | 4761.667us | 50 | 50 | 100.00 | |
| sec_cm_dai_fsm_sparse | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 146.810s | 20507.675us | 3 | 5 | 60.00 | |
| sec_cm_kdi_fsm_sparse | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 146.810s | 20507.675us | 3 | 5 | 60.00 | |
| sec_cm_lci_fsm_sparse | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 146.810s | 20507.675us | 3 | 5 | 60.00 | |
| sec_cm_part_fsm_sparse | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 146.810s | 20507.675us | 3 | 5 | 60.00 | |
| sec_cm_scrmbl_fsm_sparse | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 146.810s | 20507.675us | 3 | 5 | 60.00 | |
| sec_cm_timer_fsm_sparse | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 146.810s | 20507.675us | 3 | 5 | 60.00 | |
| sec_cm_dai_ctr_redun | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 146.810s | 20507.675us | 3 | 5 | 60.00 | |
| sec_cm_kdi_seed_ctr_redun | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 146.810s | 20507.675us | 3 | 5 | 60.00 | |
| sec_cm_kdi_entropy_ctr_redun | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 146.810s | 20507.675us | 3 | 5 | 60.00 | |
| sec_cm_lci_ctr_redun | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 146.810s | 20507.675us | 3 | 5 | 60.00 | |
| sec_cm_part_ctr_redun | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 146.810s | 20507.675us | 3 | 5 | 60.00 | |
| sec_cm_scrmbl_ctr_redun | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 146.810s | 20507.675us | 3 | 5 | 60.00 | |
| sec_cm_timer_integ_ctr_redun | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 146.810s | 20507.675us | 3 | 5 | 60.00 | |
| sec_cm_timer_cnsty_ctr_redun | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 146.810s | 20507.675us | 3 | 5 | 60.00 | |
| sec_cm_timer_lfsr_redun | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 146.810s | 20507.675us | 3 | 5 | 60.00 | |
| sec_cm_dai_fsm_local_esc | 201 | 205 | 98.05 | |||
| otp_ctrl_parallel_lc_esc | 38.870s | 12903.191us | 198 | 200 | 99.00 | |
| otp_ctrl_sec_cm | 146.810s | 20507.675us | 3 | 5 | 60.00 | |
| sec_cm_lci_fsm_local_esc | 198 | 200 | 99.00 | |||
| otp_ctrl_parallel_lc_esc | 38.870s | 12903.191us | 198 | 200 | 99.00 | |
| sec_cm_kdi_fsm_local_esc | 198 | 200 | 99.00 | |||
| otp_ctrl_parallel_lc_esc | 38.870s | 12903.191us | 198 | 200 | 99.00 | |
| sec_cm_part_fsm_local_esc | 218 | 250 | 87.20 | |||
| otp_ctrl_parallel_lc_esc | 38.870s | 12903.191us | 198 | 200 | 99.00 | |
| otp_ctrl_macro_errs | 53.030s | 5530.986us | 20 | 50 | 40.00 | |
| sec_cm_scrmbl_fsm_local_esc | 198 | 200 | 99.00 | |||
| otp_ctrl_parallel_lc_esc | 38.870s | 12903.191us | 198 | 200 | 99.00 | |
| sec_cm_timer_fsm_local_esc | 201 | 205 | 98.05 | |||
| otp_ctrl_parallel_lc_esc | 38.870s | 12903.191us | 198 | 200 | 99.00 | |
| otp_ctrl_sec_cm | 146.810s | 20507.675us | 3 | 5 | 60.00 | |
| sec_cm_dai_fsm_global_esc | 201 | 205 | 98.05 | |||
| otp_ctrl_parallel_lc_esc | 38.870s | 12903.191us | 198 | 200 | 99.00 | |
| otp_ctrl_sec_cm | 146.810s | 20507.675us | 3 | 5 | 60.00 | |
| sec_cm_lci_fsm_global_esc | 198 | 200 | 99.00 | |||
| otp_ctrl_parallel_lc_esc | 38.870s | 12903.191us | 198 | 200 | 99.00 | |
| sec_cm_kdi_fsm_global_esc | 198 | 200 | 99.00 | |||
| otp_ctrl_parallel_lc_esc | 38.870s | 12903.191us | 198 | 200 | 99.00 | |
| sec_cm_part_fsm_global_esc | 218 | 250 | 87.20 | |||
| otp_ctrl_parallel_lc_esc | 38.870s | 12903.191us | 198 | 200 | 99.00 | |
| otp_ctrl_macro_errs | 53.030s | 5530.986us | 20 | 50 | 40.00 | |
| sec_cm_scrmbl_fsm_global_esc | 198 | 200 | 99.00 | |||
| otp_ctrl_parallel_lc_esc | 38.870s | 12903.191us | 198 | 200 | 99.00 | |
| sec_cm_timer_fsm_global_esc | 201 | 205 | 98.05 | |||
| otp_ctrl_parallel_lc_esc | 38.870s | 12903.191us | 198 | 200 | 99.00 | |
| otp_ctrl_sec_cm | 146.810s | 20507.675us | 3 | 5 | 60.00 | |
| sec_cm_part_data_reg_integrity | 282 | 300 | 94.00 | |||
| otp_ctrl_init_fail | 8.050s | 1943.961us | 282 | 300 | 94.00 | |
| sec_cm_part_data_reg_bkgn_chk | 16 | 50 | 32.00 | |||
| otp_ctrl_check_fail | 24.850s | 1763.523us | 16 | 50 | 32.00 | |
| sec_cm_part_mem_regren | 50 | 50 | 100.00 | |||
| otp_ctrl_dai_lock | 64.930s | 11465.961us | 50 | 50 | 100.00 | |
| sec_cm_part_mem_sw_unreadable | 50 | 50 | 100.00 | |||
| otp_ctrl_dai_lock | 64.930s | 11465.961us | 50 | 50 | 100.00 | |
| sec_cm_part_mem_sw_unwritable | 50 | 50 | 100.00 | |||
| otp_ctrl_dai_lock | 64.930s | 11465.961us | 50 | 50 | 100.00 | |
| sec_cm_lc_part_mem_sw_noaccess | 50 | 50 | 100.00 | |||
| otp_ctrl_dai_lock | 64.930s | 11465.961us | 50 | 50 | 100.00 | |
| sec_cm_access_ctrl_mubi | 50 | 50 | 100.00 | |||
| otp_ctrl_dai_lock | 64.930s | 11465.961us | 50 | 50 | 100.00 | |
| sec_cm_token_valid_ctrl_mubi | 50 | 50 | 100.00 | |||
| otp_ctrl_smoke | 16.690s | 4761.667us | 50 | 50 | 100.00 | |
| sec_cm_lc_ctrl_intersig_mubi | 50 | 50 | 100.00 | |||
| otp_ctrl_dai_lock | 64.930s | 11465.961us | 50 | 50 | 100.00 | |
| sec_cm_test_bus_lc_gated | 50 | 50 | 100.00 | |||
| otp_ctrl_smoke | 16.690s | 4761.667us | 50 | 50 | 100.00 | |
| sec_cm_test_tl_lc_gate_fsm_sparse | 3 | 5 | 60.00 | |||
| otp_ctrl_sec_cm | 146.810s | 20507.675us | 3 | 5 | 60.00 | |
| sec_cm_direct_access_config_regwen | 50 | 50 | 100.00 | |||
| otp_ctrl_regwen | 14.100s | 1177.241us | 50 | 50 | 100.00 | |
| sec_cm_check_trigger_config_regwen | 50 | 50 | 100.00 | |||
| otp_ctrl_smoke | 16.690s | 4761.667us | 50 | 50 | 100.00 | |
| sec_cm_check_config_regwen | 50 | 50 | 100.00 | |||
| otp_ctrl_smoke | 16.690s | 4761.667us | 50 | 50 | 100.00 | |
| sec_cm_macro_mem_integrity | 20 | 50 | 40.00 | |||
| otp_ctrl_macro_errs | 53.030s | 5530.986us | 20 | 50 | 40.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| otp_ctrl_low_freq_read | 1 | 1 | 100.00 | |||
| otp_ctrl_low_freq_read | 17.140s | 5859.829us | 1 | 1 | 100.00 | |
| stress_all_with_rand_reset | 20 | 100 | 20.00 | |||
| otp_ctrl_stress_all_with_rand_reset | 173.970s | 62739.927us | 20 | 100 | 20.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Offending '(cio_test_en_o == *)' | ||||
| otp_ctrl_csr_mem_rw_with_rand_reset | 34799610538061050863844537881183985417303496371294152963561727352762455254385 | 93 |
Offending '(cio_test_en_o == 0)'
UVM_ERROR @ 87992465 ps: (otp_ctrl_if.sv:297) [ASSERT FAILED] CioTestEnOWithDftOff_A
UVM_INFO @ 87992465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_csr_mem_rw_with_rand_reset | 21684577410714150492738925845316777853239451800513375605717214951577282499125 | 93 |
Offending '(cio_test_en_o == 0)'
UVM_ERROR @ 429024914 ps: (otp_ctrl_if.sv:297) [ASSERT FAILED] CioTestEnOWithDftOff_A
UVM_INFO @ 429024914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 37031697817731033854651975569139658018081385609476092261821579420882759984841 | 93 |
Offending '(cio_test_en_o == 0)'
UVM_ERROR @ 26838970 ps: (otp_ctrl_if.sv:297) [ASSERT FAILED] CioTestEnOWithDftOff_A
UVM_INFO @ 26838970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * | ||||
| otp_ctrl_csr_mem_rw_with_rand_reset | 61527506107639618904906833876013026148298922187084089361118408168810253728793 | 92 |
UVM_ERROR @ 40758879 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 40758879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_csr_mem_rw_with_rand_reset | 32490214871585337361956695475557542014118727232922000428764651201747849931047 | 98 |
UVM_ERROR @ 119899438 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 119899438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_csr_mem_rw_with_rand_reset | 112517103169180109667585336146435362819528870892841155737032583776308953709930 | 92 |
UVM_ERROR @ 56502517 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 56502517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 110634807347275785408642893952975148493884010188516044552620869743957296937512 | 92 |
UVM_ERROR @ 34775749 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 34775749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 15811759803708234837563540321332479993624933238693465538134151919289044924557 | 186 |
UVM_ERROR @ 2356856399 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 2356856399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 101659344233350844121766802812174643618000269478694255350693039625702416699605 | 4278 |
UVM_ERROR @ 941765357 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 941765357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 102748637151089440191887863168058865756742894435597203580407214297875823441177 | 7254 |
UVM_ERROR @ 583243766 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 583243766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 7929677167568990914818561583118110472760270833127138129385170720844017529392 | 17504 |
UVM_ERROR @ 1097705756 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 1097705756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 12582356708467099627186844883760121495276613632842727152153803280311763792550 | 3549 |
UVM_ERROR @ 543684623 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 543684623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 96793205556468781132759070434329983027347703776890207278221054588254541232160 | 9560 |
UVM_ERROR @ 5155988442 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 5155988442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (otp_ctrl_scoreboard.sv:1825) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * | ||||
| otp_ctrl_csr_mem_rw_with_rand_reset | 18872957498549597083565015817660368071182690943000696380003209660547581819183 | 98 |
UVM_ERROR @ 64325710 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 64325710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 49476827964798569117715644122270044427754543919282878364303047987347663157012 | 1745 |
UVM_ERROR @ 4774644241 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 4774644241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 53783435603722327973817201633980510781472873640634149328797959744218952781099 | 92 |
UVM_ERROR @ 426730311 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 426730311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 64953778072945444958134988399899369282415337954445336487747157135300500280734 | 92 |
UVM_ERROR @ 427405120 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 427405120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 87684155016060012581170101779526649929570162678550782538700279930039776551993 | 92 |
UVM_ERROR @ 52719734 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 52719734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 76966894224440611765048666315440757550165304635990643258098101997206600095296 | 92 |
UVM_ERROR @ 54514237 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 54514237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 85143178057154031053441493413707810672634923661632495702151676279653576578895 | 92 |
UVM_ERROR @ 51556162 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 51556162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 39019401690286635587717267900540684321310279812147456135154229742986840713980 | 178 |
UVM_ERROR @ 877901418 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 877901418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 18314354479506011634865153368461175508691218575989621055292735865002486957969 | 6200 |
UVM_ERROR @ 17813598373 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 17813598373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 77304610233443864832812091337704872333422125226430855447651465237001827433481 | 1376 |
UVM_ERROR @ 106457528 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 106457528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 74047054155441500614606400202654985607971431149173578397584697366872669260994 | 16909 |
UVM_ERROR @ 1176224448 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 1176224448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 23422243094843901504706419653251849148261657923582651397198438266147619409193 | 30490 |
UVM_ERROR @ 9512929239 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 9512929239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 104531831321662458738912696264117288046397292775904655114788954147028845120420 | 92 |
UVM_ERROR @ 35211299 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 35211299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 78289319485455923241831213958202431153376026730801793919550831771143758509960 | 6204 |
UVM_ERROR @ 3164905110 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 3164905110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 35605967901617467027712383420629589570310871249155477229060689784660363758575 | 6063 |
UVM_ERROR @ 1360473218 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 1360473218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 81118021814469767316412087820525200583717366370747687504163984374430843364063 | 92 |
UVM_ERROR @ 427140428 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 427140428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 69385187690349098987203846699626064964150996359379683517555823771999002280033 | 92 |
UVM_ERROR @ 429555236 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 429555236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 22502954832642088686741662626454653904847169455341693753803794028509156086943 | 92 |
UVM_ERROR @ 60045625 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 60045625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 22696144539830194362930112388480564484089965934794163933761875472015739595863 | 7754 |
UVM_ERROR @ 4058335712 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 4058335712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 87847095945003698274818920796861214905014996739402231266531229029216668690349 | 92 |
UVM_ERROR @ 89272838 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 89272838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 89823241806641613368726323242788138137233326425948694429930730947161022014199 | 314 |
UVM_ERROR @ 155739370 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 155739370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 60420983270435280605218563468269642021891052537490649097409494115782044405810 | 2212 |
UVM_ERROR @ 17562353416 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 17562353416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 72070795028584508370450274444449795613699154933526239459944600736406116321569 | 10639 |
UVM_ERROR @ 663761968 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 663761968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 57636238991807728213697946705322439460730962053430754490564642008064297509138 | 92 |
UVM_ERROR @ 52984039 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 52984039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 64039162992756556958287047199760891253835232174229249198139083530208902494939 | 47832 |
UVM_ERROR @ 2828264198 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 2828264198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 25027436856933741343559525906766826375188512692002567120351080177734167991467 | 3781 |
UVM_ERROR @ 941941100 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 941941100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 80705845280772375028458514969627996592022501456721961512666367567501357532200 | 92 |
UVM_ERROR @ 426788328 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 426788328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 16281951411231929387326755923242305097973255283311967213864666349509640867335 | 8609 |
UVM_ERROR @ 3533468991 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 3533468991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 28014090512368395028235243898552413134490610524505294569428235115631769337058 | 9612 |
UVM_ERROR @ 65471355489 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 65471355489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 66337229002653200801272055552441368535122473840531052021707042631012313084460 | 92 |
UVM_ERROR @ 37406589 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 37406589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 81041613288169081170289361931432951236554818091509206621963114589937424399536 | 238 |
UVM_ERROR @ 223792572 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 223792572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* | ||||
| otp_ctrl_check_fail | 110589533619078072264455400760600295475348842630381423942475356636199439262358 | 4025 |
UVM_ERROR @ 1355600290 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 16384 [0x4000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 1355600290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 30347231489103995517824853628899755124291402036632950552362415320493784146888 | 237 |
UVM_ERROR @ 228252361 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (379055360 [0x1697ed00] vs 379055424 [0x1697ed40]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 228252361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 37368639022394283478145027926094283980968002522978585146104036994128001532846 | 1471 |
UVM_ERROR @ 1481425878 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3487429870 [0xcfddf4ee] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 1481425878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 75436000395839153451185797141981704753359948692089748359033323871687224364833 | 9184 |
UVM_ERROR @ 647065778 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2821503746 [0xa82cbb02] vs 4189896526 [0xf9bcbf4e]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 647065778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 33873939971538051939617685828979931518590967116177955092228667315512016510943 | 3794 |
UVM_ERROR @ 228630473 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 128 [0x80]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 228630473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 8821593458056460765227507432702169444542495856314237864541017421645473513483 | 3854 |
UVM_ERROR @ 5308657511 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 512 [0x200]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 5308657511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 108449689053036083427037915709471923835666702458401595025288065761075970849002 | 881 |
UVM_ERROR @ 216428564 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 128 [0x80]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 216428564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 54545760466705845416850755206056867582979174324666268055254902425935362995307 | 5394 |
UVM_ERROR @ 1763523390 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 256 [0x100]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 1763523390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 58873669206371315162996541047351765758961167758947095176642685478218227375377 | 159 |
UVM_ERROR @ 34120899 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1141053081 [0x44031699] vs 1141085337 [0x44039499]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 34120899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 33717860577132989025767301011032172623516405168793334085150720174373605563581 | 4853 |
UVM_ERROR @ 146253470 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 16384 [0x4000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 146253470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 38181737462653874630111893573352465372273271063479984388381196531604060780893 | 5214 |
UVM_ERROR @ 579956158 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 8 [0x8]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 579956158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 29273457589472403053704409157981393131705018666070316491715953079093908767777 | 4340 |
UVM_ERROR @ 291758622 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 512 [0x200]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 291758622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 17865907678191745535174670605598944849134546916976374561794486481871716024797 | 4225 |
UVM_ERROR @ 267435674 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (569066297 [0x21eb4339] vs 569066265 [0x21eb4319]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 267435674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 68599153548584416871096100902390452236785306273211224851794171268032634590143 | 1310 |
UVM_ERROR @ 195055671 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 8320 [0x2080]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 195055671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 90270325130450762980170870537155203742649876985400473868055889385305183368424 | 297 |
UVM_ERROR @ 64762234 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 256 [0x100]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 64762234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 114570470033130530917567716253943081873250865261729854377521472235223533350288 | 3727 |
UVM_ERROR @ 299922897 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1127082709 [0x432dead5] vs 1127082645 [0x432dea95]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 299922897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 102010453032941807450360284261939685311924703333965297416770689682079312842395 | 2605 |
UVM_ERROR @ 211070860 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 512 [0x200]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 211070860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 15332334267793526416242345611675464635427211029964206194435662428037988392595 | 3896 |
UVM_ERROR @ 1385579634 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 1385579634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 111417890290927423265170698904559083290415980012027053529057143155480676906334 | 2916 |
UVM_ERROR @ 187292447 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 512 [0x200]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 187292447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 87986935599615770916213132522125776794861304596567718636489410752754591148825 | 12117 |
UVM_ERROR @ 1734123339 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 64 [0x40]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 1734123339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 75505062052828162283392020070195001477825616379432681822777675976033444174370 | 625 |
UVM_ERROR @ 172507458 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1604008252 [0x5f9b393c] vs 1604008253 [0x5f9b393d]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 172507458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 100313274330699182992903258490090195985259477071374775796640655097500979442740 | 8212 |
UVM_ERROR @ 684594907 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 16384 [0x4000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 684594907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 8899873516636387340180717889372191178141324481647361201275095026677647473696 | 12142 |
UVM_ERROR @ 406466215 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 32768 [0x8000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 406466215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 53116413986121323310357034426333403626672606156902670928498737410045599813125 | 3252 |
UVM_ERROR @ 553804756 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (646965939 [0x268feab3] vs 646965907 [0x268fea93]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 553804756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 16848368998962900802616719986402142888188218021009715362944504147208790875329 | 453 |
UVM_ERROR @ 60964029 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 128 [0x80]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 60964029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 90363447051917060036314599490378006044577013614777024819593918139394452468529 | 1577 |
UVM_ERROR @ 120480657 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1024 [0x400]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 120480657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 7860302583321905250667768784779777387616680712584243528380910814667862673619 | 2745 |
UVM_ERROR @ 640469174 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2 [0x2]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 640469174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 102138665417494867363117134439182629983084768142465882905358366001225660957291 | 3544 |
UVM_ERROR @ 537475036 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3800948838 [0xe28de066] vs 3800948836 [0xe28de064]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 537475036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_dai_errs | 25120764838681510844251611070644908219596640462574432193386835307129622050223 | 2653 |
UVM_ERROR @ 759133855 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (362147342 [0x1595ee0e] vs 3718246239 [0xdd9fef5f]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 759133855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 47421248705691067371564840018702511390083857234597730452791548479852318869131 | 633 |
UVM_ERROR @ 148110191 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1712559186 [0x66139452] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 148110191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 89555515557646666160843778488410988293476064363091852952961503885719876476849 | 1011 |
UVM_ERROR @ 76835267 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 32768 [0x8000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 76835267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 67453264475197571171894659743348835851526190789165696410961698915550760735558 | 449 |
UVM_ERROR @ 47036500 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 256 [0x100]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 47036500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 61948209192676236741925713542644903769524450030012014203807847377090244657658 | 4340 |
UVM_ERROR @ 123013548 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 8192 [0x2000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 123013548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 74572329605345129200198973272870400927882822692083781965766725722753192611543 | 1597 |
UVM_ERROR @ 3890793650 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 32 [0x20]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 3890793650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 20220853427274716760219336581079571177201320837818669248717359625251382139499 | 2183 |
UVM_ERROR @ 323169566 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 512 [0x200]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 323169566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 73434238490135074690064589915320763227500643834498410484902161509968546679520 | 2744 |
UVM_ERROR @ 224848745 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 256 [0x100]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 224848745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 102952945574183595586859752691275118747707883502743381670172569170030489570157 | 5097 |
UVM_ERROR @ 1706929079 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2 [0x2]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 1706929079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 95133025179765204436299786265492647246857707295064054070489978224395165789645 | 8401 |
UVM_ERROR @ 22302169335 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2420901612 [0x904c06ec] vs 3505383422 [0xd0efe7fe]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 22302169335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 17455215427410182727062160414703872680992438992018900423946915678587236545569 | 813 |
UVM_ERROR @ 127633827 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 32768 [0x8000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 127633827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 74274699637428355552870731733866886214169952030209476094666669503825838402100 | 9275 |
UVM_ERROR @ 782676553 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 16384 [0x4000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 782676553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 62362423400361811384547352768863568066042827092364807892289837221033241068053 | 5939 |
UVM_ERROR @ 2041884951 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4211538914 [0xfb06fbe2] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 2041884951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 31953183872690855454675360752238496026731549480291157152356938949415213395206 | 3249 |
UVM_ERROR @ 638015369 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 16640 [0x4100]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 638015369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 33030556119137503846131319099839595730222428559978258643285265174346357376750 | 10842 |
UVM_ERROR @ 625546959 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 8 [0x8]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 625546959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 94961923635575918553234787122679657148171807084394134095227333684986803979366 | 4255 |
UVM_ERROR @ 1193524279 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2828967108 [0xa89e9cc4] vs 2828966086 [0xa89e98c6]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 1193524279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 17639008993942252873089280619102854903586326372876030515805315303406699736042 | 459 |
UVM_ERROR @ 81299461 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 16384 [0x4000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 81299461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 43809049810168241825740457026343694663856132219950396159269248800786075856518 | 3084 |
UVM_ERROR @ 387301342 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1306310580 [0x4ddcb7b4] vs 1306310644 [0x4ddcb7f4]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 387301342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_dai_errs | 89251501362405595385647208547082011832458941275015531945056974956114389809144 | 2621 |
UVM_ERROR @ 1989897287 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3124028299 [0xba34e38b] vs 3207918479 [0xbf34f38f]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 1989897287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 3003415864820535850571047245246489154490056713512637473680414210037727667128 | 617 |
UVM_ERROR @ 1629080379 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 256 [0x100]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 1629080379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 61843550813485995124560379839305928117482766325414650997800508281949766306413 | 325 |
UVM_ERROR @ 121158345 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 66 [0x42]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 121158345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 106637539150960861025124542790573485394863147587022771691374257990779370506836 | 165 |
UVM_ERROR @ 507752096 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 32 [0x20]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 507752096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 59610617301927983194597768839741115529194966949167119569508060893974229615937 | 5532 |
UVM_ERROR @ 11995542191 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2048 [0x800]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 11995542191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 50545385567189415088121237767167948787864311068266807150848866157064183363933 | 7592 |
UVM_ERROR @ 492831110 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 272 [0x110]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 492831110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 87498612958386529631224040489383880686637333996234358087462796888667674073384 | 4507 |
UVM_ERROR @ 805533291 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 8 [0x8]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 805533291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 74520758361032154371188841949495804111856545575972890193222953695360283662002 | 34714 |
UVM_ERROR @ 12704588524 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 4294967167 [0xffffff7f]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 12704588524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 13126846380857494712983718059196391472731088068259752437841849762051689844768 | 2695 |
UVM_ERROR @ 133416469 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 16 [0x10]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 133416469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 87356296887627255999381491272728575998122223456793593248688725489141446763029 | 3410 |
UVM_ERROR @ 525806593 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 128 [0x80]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 525806593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 92747115537381306884732303067071239229085286655176214087625383964802248246222 | 10390 |
UVM_ERROR @ 739700688 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (365797670 [0x15cda126] vs 365797382 [0x15cda006]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 739700688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 68957759947750991710060283717649191318949716679027109039266535850052461758953 | 2167 |
UVM_ERROR @ 1005322343 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2514892418 [0x95e63682] vs 2514888322 [0x95e62682]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 1005322343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 59570552855816975194244555371543189497817414614364545343282327346540057045716 | 409 |
UVM_ERROR @ 118974431 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1024 [0x400]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 118974431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 74522728610210528376680662918580622452589082185493737177309169688548069183903 | 4219 |
UVM_ERROR @ 388489585 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2052 [0x804]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 388489585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 11032855407492308736303463421195484393065475172470728516316223028255011539773 | 583 |
UVM_ERROR @ 1340658526 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 4096 [0x1000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 1340658526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 48280592726306207935214480210415435634623994435694455618846225460886185072389 | 4475 |
UVM_ERROR @ 190230591 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 256 [0x100]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 190230591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 3155919747686078930429262005430446284157183288853100216477089195572166444418 | 335 |
UVM_ERROR @ 79025807 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 32 [0x20]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 79025807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 44011762325497548794379236525656248935344113466625304021781854866588299870665 | 25435 |
UVM_ERROR @ 2840834517 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3174898400 [0xbd3d1ae0] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 2840834517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 71072815949001958136427878424772364139517804355432787143662704083017689407597 | 5889 |
UVM_ERROR @ 895630111 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3358361592 [0xc82c87f8] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 895630111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 62303918610623548022690414908478135194410623596482768153264632955350131665123 | 213 |
UVM_ERROR @ 34435306 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (343597196 [0x147ae08c] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 34435306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 101501707445564181161992997619043786339345636319161913134126719458345606220652 | 9063 |
UVM_ERROR @ 9763833530 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3410305672 [0xcb452288] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 9763833530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 6201373958060446675116272723046485626855452705306801781384083016226721143075 | 7835 |
UVM_ERROR @ 3471162817 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3518834357 [0xd1bd26b5] vs 4257199799 [0xfdbfb6b7]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 3471162817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 96902543396113201715148696983905055321154900245987371392237874781079192451999 | 14256 |
UVM_ERROR @ 6288931979 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3324347059 [0xc62582b3] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 6288931979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 23114157020896928432245034232870992013782327515100211065071912602903154319566 | 18048 |
UVM_ERROR @ 981970504 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3529866429 [0xd2657cbd] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 981970504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 80976607708260678567483004930152062474590116850075483685427481502895007121980 | 16706 |
UVM_ERROR @ 43707799907 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1778925112 [0x6a083e38] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 43707799907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 38825854725946457299831504207831195441265207651840526931530771420515073036713 | 7968 |
UVM_ERROR @ 704063686 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (455050217 [0x1b1f83e9] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 704063686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 11578422920924061424871978172528906416920602225115870192163851984562336355124 | 3368 |
UVM_ERROR @ 3949385868 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2538972605 [0x9755a5bd] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 3949385868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 65788519897435140967779548990651802167947134048109743708422696821374397931666 | 13554 |
UVM_ERROR @ 11438503017 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1871057712 [0x6f861330] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 11438503017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 10959756393242141233572691355965396173110443989467893553478320137331504283441 | 1971 |
UVM_ERROR @ 4526068505 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2943486412 [0xaf7209cc] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 4526068505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 41418030329529787356117812681179454302045486309345264065466834460806656673896 | 1311 |
UVM_ERROR @ 2872143079 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3066580357 [0xb6c84d85] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 2872143079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 111790321856978022329466915242626691202512328154565224955766480613135606443524 | 1189 |
UVM_ERROR @ 809262002 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (601986402 [0x23e19562] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 809262002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 22723320599428966294352866075282836466818838834585197281844494701666825444142 | 23013 |
UVM_ERROR @ 60580871466 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1108051609 [0x420b8699] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 60580871466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [otp_ctrl_common_vseq] expect alert:fatal_check_error to fire | ||||
| otp_ctrl_sec_cm | 13350458331499408451577913959388919132759586253968412665030944509100834194029 | 1381 |
UVM_ERROR @ 10138043134 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] expect alert:fatal_check_error to fire
UVM_INFO @ 10138043134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_sec_cm | 45748799894599018639930797118358562769743556474620819646728805617797008310467 | 1484 |
UVM_ERROR @ 5177133406 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] expect alert:fatal_check_error to fire
UVM_INFO @ 5177133406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:1315) [otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_check_error does not trigger! | ||||
| otp_ctrl_stress_all_with_rand_reset | 10346914690219883441688438095792503864916982638427901290819823005152742293782 | 7493 |
UVM_ERROR @ 5828076577 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 5828076577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 55914176255203544930426732252062945220490777067060851818785147031608629907131 | 27402 |
UVM_ERROR @ 24512506602 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 24512506602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 106046857880604978625587131942827248151034526980781372146691638691323138077946 | 57274 |
UVM_ERROR @ 12037686255 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 12037686255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 37454160294335797665726166486916401942527352890036121663590900808127441851063 | 23646 |
UVM_ERROR @ 13897083965 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 13897083965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 94711814834066675702860290433455931006300968993515039718874409126440467713399 | 81373 |
UVM_ERROR @ 39954344242 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 39954344242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 29861561428124843163967538591962461752984267050149436741383449399194515205717 | 4496 |
UVM_ERROR @ 5947935751 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 5947935751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 62972558666622994410671491406588837451168668931740068154190336497132054902286 | 90499 |
UVM_ERROR @ 5131913981 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 5131913981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 5932963047732663846422482399365300625626252272583403764162265015884694791191 | 8710 |
UVM_ERROR @ 6905504118 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 6905504118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 21047103763695615554157725303770779027760702893896062404468902255250988818563 | 56508 |
UVM_ERROR @ 26872128747 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 26872128747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 74731487632986803529856777728751586689155404700874143923624398457340721156965 | 56455 |
UVM_ERROR @ 35779630978 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 35779630978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 24277207839487621505774849823992980330266391317789081725637678007284731470022 | 19341 |
UVM_ERROR @ 15698401280 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 15698401280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 65669978035736474395365731950746270238610488047507114134655768234534296203906 | 11799 |
UVM_ERROR @ 42712662679 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 42712662679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 34884387142093422065015891120238646552401551856084344261846460813606778082524 | 59723 |
UVM_ERROR @ 6033596759 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 6033596759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 25120880742250187412429048810178132077717466713397335735081984447062580538505 | 11320 |
UVM_ERROR @ 1332350392 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 1332350392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 36462567423777692179313729292708767149764861565048189596730893765416487622154 | 6537 |
UVM_ERROR @ 874840822 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 874840822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 16490904786421300996961558105961851714788206564206486768226702840094579132614 | 5474 |
UVM_ERROR @ 1620664153 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 1620664153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:1315) [otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_check_error does not trigger! | ||||
| otp_ctrl_init_fail | 10112105471659308080196124115666132230530567374439165469488624007070807501699 | 1783 |
UVM_ERROR @ 411187019 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 411187019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 47187911319972809608447481499111058217463521770722432608736049949354261260990 | 2109 |
UVM_ERROR @ 505112746 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 505112746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 93842594916870610462215808606876241116860635911259565026151227050979997823495 | 1753 |
UVM_ERROR @ 1897030704 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 1897030704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 47686904675768895803377000256290171745996695183724074425026122006819138478976 | 1119 |
UVM_ERROR @ 1646405274 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 1646405274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 37525686938404705261886098069860718040430390683181427794523798588073849313693 | 1373 |
UVM_ERROR @ 287407116 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 287407116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 33413804171794571658518308065144739818213113670170626973769904196662515923152 | 1559 |
UVM_ERROR @ 531121809 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 531121809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 46602414855201168393715727796040826742238431229264205317250780400515886076177 | 1671 |
UVM_ERROR @ 240751398 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 240751398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 14736060525699192399357627771155818619182168247318614195677812826550430480667 | 1779 |
UVM_ERROR @ 1615433611 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 1615433611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 104297364048597502790866492585939282454681113477813515204816333892109565062284 | 2039 |
UVM_ERROR @ 143084593 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 143084593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 99551408374534015236252185372727287666842653881829819110831600330707587600971 | 1181 |
UVM_ERROR @ 1575443503 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 1575443503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 39524195217515831158430692597458002641291522476529907660959468271865606500357 | 2733 |
UVM_ERROR @ 1467849328 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 1467849328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 101274487647570272223168078212688307961732000820404196328655523833531873280414 | 1963 |
UVM_ERROR @ 151719533 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 151719533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 81287163824822536286661001840734330608132369122293176547731320324462794588443 | 1337 |
UVM_ERROR @ 724713526 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 724713526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 37414307153093005369593797527612180383217092097985457017671092902080019011389 | 1413 |
UVM_ERROR @ 1665182316 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 1665182316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 98217621032302194790282245464515357391353264103445318251992895058454230733333 | 1193 |
UVM_ERROR @ 1527947402 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 1527947402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 91552689922937711592227797973902875581986635331917524148270899932956455983385 | 2769 |
UVM_ERROR @ 317810812 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 317810812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 30534253704036893526212657936735256027622676482300284091622881074248700695348 | 1641 |
UVM_ERROR @ 2189761215 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 2189761215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state | ||||
| otp_ctrl_stress_all_with_rand_reset | 101469839913358305025817840054048973268176339488365056770356972531651360815912 | 13853 |
UVM_ERROR @ 5955107673 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
UVM_INFO @ 5955107673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 16777270925090723085554597192774180467051703652646319596010625737007933432004 | 2805 |
UVM_ERROR @ 1245707673 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
UVM_INFO @ 1245707673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 48104937290076076996252378288872140794727215727802486948346162742078981268642 | 16492 |
UVM_ERROR @ 17407831965 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
UVM_INFO @ 17407831965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 36639069576922501152899038035418767528787263038717187266388630450655278374888 | 12927 |
UVM_ERROR @ 53636719286 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
UVM_INFO @ 53636719286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 31835706916516901720401505653230919585385826322643755265308951817361510060848 | 3509 |
UVM_ERROR @ 1022931042 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
UVM_INFO @ 1022931042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 24836282041965617745135153548206909724591486841662842159296590574561960693297 | 3390 |
UVM_ERROR @ 2692364247 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3 [0x3] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
UVM_INFO @ 2692364247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 49387638626051719989862417814764276564806377716291897365211032880097094804513 | 12673 |
UVM_ERROR @ 7409311217 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
UVM_INFO @ 7409311217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 70765415062609886999592441581649173492984573587870881675967657574049012394478 | 6168 |
UVM_ERROR @ 3677778419 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
UVM_INFO @ 3677778419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 11479298964348668959854523322168431805738553936383596414798614650111025229586 | 4432 |
UVM_ERROR @ 299043835 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3 [0x3] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
UVM_INFO @ 299043835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 54232205777303547689599703073994555593833184805388788782076856735250964680888 | 924 |
UVM_ERROR @ 9402779603 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
UVM_INFO @ 9402779603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 72318281263174798974599481677114760680777459273629299296381679732778782930314 | 9261 |
UVM_ERROR @ 3267375148 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
UVM_INFO @ 3267375148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 110085360357489315865819034274044617613999538207184018077022778248904170981908 | 15179 |
UVM_ERROR @ 3049476827 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
UVM_INFO @ 3049476827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 85440876561162534214897818487676480817411040245481517468787441048863868545412 | 14751 |
UVM_ERROR @ 1521585281 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
UVM_INFO @ 1521585281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 105734321190133726585938214779452766048708731042050671814524330348508629949089 | 639 |
UVM_ERROR @ 97167550 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
UVM_INFO @ 97167550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 29994403375744997488253075384844042526737302630529985646150023130500451758179 | 31323 |
UVM_ERROR @ 8205343078 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
UVM_INFO @ 8205343078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 20142004053381133628108623727332131042904302060073812745659414885059296891239 | 18245 |
UVM_ERROR @ 10991019604 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
UVM_INFO @ 10991019604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (otp_ctrl_scoreboard.sv:691) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: OtpErr | ||||
| otp_ctrl_check_fail | 60398503465783988337325915025948715665714498278232811330340810049661002730628 | 3181 |
UVM_ERROR @ 120442444 ps: (otp_ctrl_scoreboard.sv:691) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x0 [0] vs 0x1 [1]) Interrupt_pin: OtpErr
UVM_INFO @ 120442444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 105982320494364245112329784930927917047419640569822195195591320019326467665633 | 1856 |
UVM_ERROR @ 166594121 ps: (otp_ctrl_scoreboard.sv:691) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x0 [0] vs 0x1 [1]) Interrupt_pin: OtpErr
UVM_INFO @ 166594121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 97784803391437397139727952400173019752839822353730651501886632480397621550782 | 7643 |
UVM_ERROR @ 13047323186 ps: (otp_ctrl_scoreboard.sv:691) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x0 [0] vs 0x1 [1]) Interrupt_pin: OtpErr
UVM_INFO @ 13047323186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert fatal_macro_error did not trigger max_delay:* | ||||
| otp_ctrl_macro_errs | 28024821401235892200870317447483957152057126414018980788083041889976356302690 | 5966 |
UVM_ERROR @ 740439460 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_macro_error did not trigger max_delay:20
UVM_INFO @ 740439460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| otp_ctrl_macro_errs | 56524175735062565742704828043837466894938654982320397462664068860285979736317 | 4671 |
UVM_ERROR @ 2248215405 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_macro_error did not trigger max_delay:20
UVM_INFO @ 2248215405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| otp_ctrl_macro_errs | 76067125696053255751707840636537938614030982340594963836609436432492987667570 | 179 |
UVM_ERROR @ 120840324 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_macro_error did not trigger max_delay:20
UVM_INFO @ 120840324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
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| otp_ctrl_macro_errs | 72880231888953869382689915236052589013907266017950368983645881232948660172360 | 3166 |
UVM_ERROR @ 636010223 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_macro_error did not trigger max_delay:20
UVM_INFO @ 636010223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch | ||||
| otp_ctrl_stress_all_with_rand_reset | 13376122607615646355773011820635684274238129863880780161951972538341224638643 | 22494 |
UVM_ERROR @ 7872000930 ps: (otp_ctrl_base_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 872 [0x368]) dai addr 368 rdata0 readout mismatch
UVM_INFO @ 7872000930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr d* rdata* readout mismatch | ||||
| otp_ctrl_stress_all_with_rand_reset | 105022213983697882010208178250993429493901757203222981871906619157259842996402 | 12845 |
UVM_ERROR @ 26371342198 ps: (otp_ctrl_base_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 212 [0xd4]) dai addr d4 rdata0 readout mismatch
UVM_INFO @ 26371342198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_FATAL (alert_receiver_driver.sv:218) [driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q | ||||
| otp_ctrl_parallel_lc_esc | 36182856224721933519331790210721741096856730544082989122063544557812328177091 | 5771 |
UVM_FATAL @ 307969062 ps: (alert_receiver_driver.sv:218) [uvm_test_top.env.m_alert_agent_fatal_check_error.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
UVM_INFO @ 307969062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| otp_ctrl_parallel_lc_esc | 74468761329654635342243001912101561054804850061940539704137029461484936410562 | 8845 |
UVM_FATAL @ 136317754 ps: (alert_receiver_driver.sv:218) [uvm_test_top.env.m_alert_agent_fatal_check_error.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
UVM_INFO @ 136317754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| otp_ctrl_init_fail | 108904167656531392075189015478361727832580373405952864337584370551497506175817 | 1781 |
UVM_FATAL @ 207796147 ps: (alert_receiver_driver.sv:218) [uvm_test_top.env.m_alert_agent_fatal_macro_error.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
UVM_INFO @ 207796147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
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| UVM_ERROR (otp_ctrl_scoreboard.sv:277) [scoreboard] Check failed exp_alert != OtpNoAlert (* [*] vs * [*]) | ||||
| otp_ctrl_stress_all_with_rand_reset | 115323050460692340279370915390181557440914018282052002258996746911765546721728 | 12011 |
UVM_ERROR @ 12646610979 ps: (otp_ctrl_scoreboard.sv:277) [uvm_test_top.env.scoreboard] Check failed exp_alert != OtpNoAlert (0 [0x0] vs 0 [0x0])
UVM_INFO @ 12646610979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *c rdata* readout mismatch | ||||
| otp_ctrl_stress_all_with_rand_reset | 62693041147479960693449957384752075367551211475932825134680582286305443928043 | 244 |
UVM_ERROR @ 1282454189 ps: (otp_ctrl_base_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 108 [0x6c]) dai addr 6c rdata0 readout mismatch
UVM_INFO @ 1282454189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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