Simulation Results

Simulation Results: rom_ctrl/32kb

25/04/2026 09:02:00 DVSim: v1.17.3 sha: 8007f61 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
98.64 %

code
99.68 %

assert
96.95 %

func
99.28 %

line
99.59 %

branch
100.00 %

cond
98.81 %

toggle
100.00 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		100.00%
V2S		94.20%
V3		100.00%

67/67 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				2	2	100.00
	rom_ctrl_smoke	10.280s	558.233us	2	2	100.00
csr_hw_reset				5	5	100.00
	rom_ctrl_csr_hw_reset	11.500s	178.201us	5	5	100.00
csr_rw				20	20	100.00
	rom_ctrl_csr_rw	9.180s	736.867us	20	20	100.00
csr_bit_bash				5	5	100.00
	rom_ctrl_csr_bit_bash	7.310s	173.532us	5	5	100.00
csr_aliasing				5	5	100.00
	rom_ctrl_csr_aliasing	6.570s	2005.578us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	rom_ctrl_csr_mem_rw_with_rand_reset	8.050s	176.687us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	rom_ctrl_csr_rw	9.180s	736.867us	20	20	100.00
	rom_ctrl_csr_aliasing	6.570s	2005.578us	5	5	100.00
mem_walk				5	5	100.00
	rom_ctrl_mem_walk	6.650s	168.741us	5	5	100.00
mem_partial_access				5	5	100.00
	rom_ctrl_mem_partial_access	6.580s	166.121us	5	5	100.00

144/144 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
max_throughput_chk				2	2	100.00
	rom_ctrl_max_throughput_chk	7.650s	197.061us	2	2	100.00
stress_all				20	20	100.00
	rom_ctrl_stress_all	28.830s	7976.335us	20	20	100.00
kmac_err_chk				2	2	100.00
	rom_ctrl_kmac_err_chk	10.040s	1819.196us	2	2	100.00
alert_test				50	50	100.00
	rom_ctrl_alert_test	7.210s	548.186us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	rom_ctrl_tl_errors	11.840s	1024.199us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	rom_ctrl_tl_errors	11.840s	1024.199us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	rom_ctrl_csr_hw_reset	11.500s	178.201us	5	5	100.00
	rom_ctrl_csr_rw	9.180s	736.867us	20	20	100.00
	rom_ctrl_csr_aliasing	6.570s	2005.578us	5	5	100.00
	rom_ctrl_same_csr_outstanding	9.620s	189.156us	20	20	100.00
tl_d_partial_access				50	50	100.00
	rom_ctrl_csr_hw_reset	11.500s	178.201us	5	5	100.00
	rom_ctrl_csr_rw	9.180s	736.867us	20	20	100.00
	rom_ctrl_csr_aliasing	6.570s	2005.578us	5	5	100.00
	rom_ctrl_same_csr_outstanding	9.620s	189.156us	20	20	100.00

V2S

65/69 passed

94.20 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
corrupt_sig_fatal_chk				16	20	80.00
	rom_ctrl_corrupt_sig_fatal_chk	151.630s	26774.350us	16	20	80.00
passthru_mem_tl_intg_err				20	20	100.00
	rom_ctrl_passthru_mem_tl_intg_err	30.380s	12533.187us	20	20	100.00
tl_intg_err				25	25	100.00
	rom_ctrl_tl_intg_err	62.740s	465.570us	20	20	100.00
	rom_ctrl_sec_cm	250.710s	493.836us	5	5	100.00
prim_fsm_check				5	5	100.00
	rom_ctrl_sec_cm	250.710s	493.836us	5	5	100.00
prim_count_check				5	5	100.00
	rom_ctrl_sec_cm	250.710s	493.836us	5	5	100.00
sec_cm_checker_ctr_consistency				16	20	80.00
	rom_ctrl_corrupt_sig_fatal_chk	151.630s	26774.350us	16	20	80.00
sec_cm_checker_ctrl_flow_consistency				16	20	80.00
	rom_ctrl_corrupt_sig_fatal_chk	151.630s	26774.350us	16	20	80.00
sec_cm_checker_fsm_local_esc				16	20	80.00
	rom_ctrl_corrupt_sig_fatal_chk	151.630s	26774.350us	16	20	80.00
sec_cm_compare_ctrl_flow_consistency				16	20	80.00
	rom_ctrl_corrupt_sig_fatal_chk	151.630s	26774.350us	16	20	80.00
sec_cm_compare_ctr_consistency				16	20	80.00
	rom_ctrl_corrupt_sig_fatal_chk	151.630s	26774.350us	16	20	80.00
sec_cm_compare_ctr_redun				5	5	100.00
	rom_ctrl_sec_cm	250.710s	493.836us	5	5	100.00
sec_cm_fsm_sparse				5	5	100.00
	rom_ctrl_sec_cm	250.710s	493.836us	5	5	100.00
sec_cm_mem_scramble				2	2	100.00
	rom_ctrl_smoke	10.280s	558.233us	2	2	100.00
sec_cm_mem_digest				2	2	100.00
	rom_ctrl_smoke	10.280s	558.233us	2	2	100.00
sec_cm_intersig_mubi				2	2	100.00
	rom_ctrl_smoke	10.280s	558.233us	2	2	100.00
sec_cm_bus_integrity				20	20	100.00
	rom_ctrl_tl_intg_err	62.740s	465.570us	20	20	100.00
sec_cm_bus_local_esc				18	22	81.82
	rom_ctrl_corrupt_sig_fatal_chk	151.630s	26774.350us	16	20	80.00
	rom_ctrl_kmac_err_chk	10.040s	1819.196us	2	2	100.00
sec_cm_mux_mubi				16	20	80.00
	rom_ctrl_corrupt_sig_fatal_chk	151.630s	26774.350us	16	20	80.00
sec_cm_mux_consistency				16	20	80.00
	rom_ctrl_corrupt_sig_fatal_chk	151.630s	26774.350us	16	20	80.00
sec_cm_ctrl_redun				16	20	80.00
	rom_ctrl_corrupt_sig_fatal_chk	151.630s	26774.350us	16	20	80.00
sec_cm_ctrl_mem_integrity				20	20	100.00
	rom_ctrl_passthru_mem_tl_intg_err	30.380s	12533.187us	20	20	100.00
sec_cm_tlul_fifo_ctr_redun				5	5	100.00
	rom_ctrl_sec_cm	250.710s	493.836us	5	5	100.00

20/20 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				20	20	100.00
	rom_ctrl_stress_all_with_rand_reset	366.830s	7717.990us	20	20	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
	rom_ctrl_corrupt_sig_fatal_chk	73964018710072191965819850732818277682047323002654633892697065836408268374741	88	UVM_ERROR @ 5051047242 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) UVM_INFO @ 5051047242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	38594531822121065200039462630071314400449145711079551516103834418027521400058	100	UVM_ERROR @ 4275104210 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) UVM_INFO @ 4275104210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	107689174800063705214278590993562581193373811985108652638868404847953418228560	105	UVM_ERROR @ 4997004996 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) UVM_INFO @ 4997004996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	11052130698932686593616458858036199240237556638035124228546048733930021788984	99	UVM_ERROR @ 4109476759 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) UVM_INFO @ 4109476759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---