Simulation Results: rom_ctrl/64kb

 
25/04/2026 09:02:00 DVSim: v1.17.3 sha: 8007f61 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.52 %
  • code
  • 99.49 %
  • assert
  • 96.80 %
  • func
  • 99.28 %
  • line
  • 99.59 %
  • branch
  • 99.64 %
  • cond
  • 98.22 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 12.060s 308.287us 2 2 100.00
csr_hw_reset 5 5 100.00
rom_ctrl_csr_hw_reset 17.060s 645.780us 5 5 100.00
csr_rw 20 20 100.00
rom_ctrl_csr_rw 12.710s 298.558us 20 20 100.00
csr_bit_bash 5 5 100.00
rom_ctrl_csr_bit_bash 10.720s 289.322us 5 5 100.00
csr_aliasing 5 5 100.00
rom_ctrl_csr_aliasing 12.270s 292.867us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 14.330s 304.657us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rom_ctrl_csr_rw 12.710s 298.558us 20 20 100.00
rom_ctrl_csr_aliasing 12.270s 292.867us 5 5 100.00
mem_walk 5 5 100.00
rom_ctrl_mem_walk 14.230s 1063.305us 5 5 100.00
mem_partial_access 5 5 100.00
rom_ctrl_mem_partial_access 14.310s 2006.361us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 12.310s 583.842us 2 2 100.00
stress_all 20 20 100.00
rom_ctrl_stress_all 55.050s 1105.153us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 17.210s 558.240us 2 2 100.00
alert_test 50 50 100.00
rom_ctrl_alert_test 18.100s 1059.456us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rom_ctrl_tl_errors 14.730s 532.096us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rom_ctrl_tl_errors 14.730s 532.096us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rom_ctrl_csr_hw_reset 17.060s 645.780us 5 5 100.00
rom_ctrl_csr_rw 12.710s 298.558us 20 20 100.00
rom_ctrl_csr_aliasing 12.270s 292.867us 5 5 100.00
rom_ctrl_same_csr_outstanding 14.830s 297.099us 20 20 100.00
tl_d_partial_access 50 50 100.00
rom_ctrl_csr_hw_reset 17.060s 645.780us 5 5 100.00
rom_ctrl_csr_rw 12.710s 298.558us 20 20 100.00
rom_ctrl_csr_aliasing 12.270s 292.867us 5 5 100.00
rom_ctrl_same_csr_outstanding 14.830s 297.099us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 277.940s 7756.347us 20 20 100.00
passthru_mem_tl_intg_err 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 71.060s 6389.129us 20 20 100.00
tl_intg_err 25 25 100.00
rom_ctrl_tl_intg_err 151.710s 1435.252us 20 20 100.00
rom_ctrl_sec_cm 612.660s 1824.662us 5 5 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 612.660s 1824.662us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 612.660s 1824.662us 5 5 100.00
sec_cm_checker_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 277.940s 7756.347us 20 20 100.00
sec_cm_checker_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 277.940s 7756.347us 20 20 100.00
sec_cm_checker_fsm_local_esc 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 277.940s 7756.347us 20 20 100.00
sec_cm_compare_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 277.940s 7756.347us 20 20 100.00
sec_cm_compare_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 277.940s 7756.347us 20 20 100.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 612.660s 1824.662us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 612.660s 1824.662us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 12.060s 308.287us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 12.060s 308.287us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 12.060s 308.287us 2 2 100.00
sec_cm_bus_integrity 20 20 100.00
rom_ctrl_tl_intg_err 151.710s 1435.252us 20 20 100.00
sec_cm_bus_local_esc 22 22 100.00
rom_ctrl_corrupt_sig_fatal_chk 277.940s 7756.347us 20 20 100.00
rom_ctrl_kmac_err_chk 17.210s 558.240us 2 2 100.00
sec_cm_mux_mubi 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 277.940s 7756.347us 20 20 100.00
sec_cm_mux_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 277.940s 7756.347us 20 20 100.00
sec_cm_ctrl_redun 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 277.940s 7756.347us 20 20 100.00
sec_cm_ctrl_mem_integrity 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 71.060s 6389.129us 20 20 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 612.660s 1824.662us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 20 20 100.00
rom_ctrl_stress_all_with_rand_reset 351.830s 3626.611us 20 20 100.00