Simulation Results: rstmgr

 
25/04/2026 09:02:00 DVSim: v1.17.3 sha: 8007f61 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.86 %
  • code
  • 99.68 %
  • assert
  • 98.13 %
  • func
  • 98.76 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 99.38 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
rstmgr_smoke 2.330s 246.956us 50 50 100.00
csr_hw_reset 5 5 100.00
rstmgr_csr_hw_reset 1.320s 121.366us 5 5 100.00
csr_rw 20 20 100.00
rstmgr_csr_rw 1.370s 92.243us 20 20 100.00
csr_bit_bash 5 5 100.00
rstmgr_csr_bit_bash 8.950s 2303.795us 5 5 100.00
csr_aliasing 5 5 100.00
rstmgr_csr_aliasing 2.370s 264.911us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rstmgr_csr_mem_rw_with_rand_reset 2.120s 184.292us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rstmgr_csr_rw 1.370s 92.243us 20 20 100.00
rstmgr_csr_aliasing 2.370s 264.911us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 50 50 100.00
rstmgr_por_stretcher 1.630s 246.991us 50 50 100.00
sw_rst 50 50 100.00
rstmgr_sw_rst 3.740s 480.373us 50 50 100.00
sw_rst_reset_race 50 50 100.00
rstmgr_sw_rst_reset_race 1.990s 221.399us 50 50 100.00
reset_info 50 50 100.00
rstmgr_reset 10.870s 1830.082us 50 50 100.00
cpu_info 50 50 100.00
rstmgr_reset 10.870s 1830.082us 50 50 100.00
alert_info 50 50 100.00
rstmgr_reset 10.870s 1830.082us 50 50 100.00
reset_info_capture 50 50 100.00
rstmgr_reset 10.870s 1830.082us 50 50 100.00
stress_all 50 50 100.00
rstmgr_stress_all 54.990s 13375.839us 50 50 100.00
alert_test 50 50 100.00
rstmgr_alert_test 1.260s 103.957us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rstmgr_tl_errors 4.860s 499.987us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rstmgr_tl_errors 4.860s 499.987us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rstmgr_csr_hw_reset 1.320s 121.366us 5 5 100.00
rstmgr_csr_rw 1.370s 92.243us 20 20 100.00
rstmgr_csr_aliasing 2.370s 264.911us 5 5 100.00
rstmgr_same_csr_outstanding 2.400s 280.624us 20 20 100.00
tl_d_partial_access 50 50 100.00
rstmgr_csr_hw_reset 1.320s 121.366us 5 5 100.00
rstmgr_csr_rw 1.370s 92.243us 20 20 100.00
rstmgr_csr_aliasing 2.370s 264.911us 5 5 100.00
rstmgr_same_csr_outstanding 2.400s 280.624us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
rstmgr_tl_intg_err 3.950s 829.460us 20 20 100.00
rstmgr_sec_cm 49.510s 16815.371us 5 5 100.00
prim_count_check 5 5 100.00
rstmgr_sec_cm 49.510s 16815.371us 5 5 100.00
prim_fsm_check 5 5 100.00
rstmgr_sec_cm 49.510s 16815.371us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
rstmgr_tl_intg_err 3.950s 829.460us 20 20 100.00
sec_cm_scan_intersig_mubi 50 50 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.790s 182.907us 50 50 100.00
sec_cm_leaf_rst_bkgn_chk 50 50 100.00
rstmgr_leaf_rst_cnsty 13.080s 2467.101us 50 50 100.00
sec_cm_leaf_rst_shadow 50 50 100.00
rstmgr_leaf_rst_shadow_attack 1.940s 302.066us 50 50 100.00
sec_cm_leaf_fsm_sparse 5 5 100.00
rstmgr_sec_cm 49.510s 16815.371us 5 5 100.00
sec_cm_sw_rst_config_regwen 20 20 100.00
rstmgr_csr_rw 1.370s 92.243us 20 20 100.00
sec_cm_dump_ctrl_config_regwen 20 20 100.00
rstmgr_csr_rw 1.370s 92.243us 20 20 100.00