| V1 |
|
100.00% |
| V2 |
|
91.67% |
| V2S |
|
100.00% |
| V3 |
|
45.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random | 20 | 20 | 100.00 | |||
| rv_timer_random | 2.250s | 152.942us | 20 | 20 | 100.00 | |
| csr_hw_reset | 5 | 5 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.910s | 68.745us | 5 | 5 | 100.00 | |
| csr_rw | 20 | 20 | 100.00 | |||
| rv_timer_csr_rw | 0.910s | 14.222us | 20 | 20 | 100.00 | |
| csr_bit_bash | 5 | 5 | 100.00 | |||
| rv_timer_csr_bit_bash | 2.430s | 94.596us | 5 | 5 | 100.00 | |
| csr_aliasing | 5 | 5 | 100.00 | |||
| rv_timer_csr_aliasing | 1.140s | 178.547us | 5 | 5 | 100.00 | |
| csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 | |||
| rv_timer_csr_mem_rw_with_rand_reset | 2.010s | 123.798us | 20 | 20 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 25 | 25 | 100.00 | |||
| rv_timer_csr_rw | 0.910s | 14.222us | 20 | 20 | 100.00 | |
| rv_timer_csr_aliasing | 1.140s | 178.547us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random_reset | 0 | 20 | 0.00 | |||
| rv_timer_random_reset | 3.430s | 870.665us | 0 | 20 | 0.00 | |
| disabled | 20 | 20 | 100.00 | |||
| rv_timer_disabled | 7.050s | 3375.215us | 20 | 20 | 100.00 | |
| cfg_update_on_fly | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 1087.690s | 2336253.571us | 10 | 10 | 100.00 | |
| no_interrupt_test | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 1087.690s | 2336253.571us | 10 | 10 | 100.00 | |
| stress | 20 | 20 | 100.00 | |||
| rv_timer_stress_all | 9.710s | 5437.264us | 20 | 20 | 100.00 | |
| alert_test | 50 | 50 | 100.00 | |||
| rv_timer_alert_test | 0.890s | 102.711us | 50 | 50 | 100.00 | |
| intr_test | 50 | 50 | 100.00 | |||
| rv_timer_intr_test | 0.890s | 53.040us | 50 | 50 | 100.00 | |
| tl_d_oob_addr_access | 20 | 20 | 100.00 | |||
| rv_timer_tl_errors | 2.740s | 495.829us | 20 | 20 | 100.00 | |
| tl_d_illegal_access | 20 | 20 | 100.00 | |||
| rv_timer_tl_errors | 2.740s | 495.829us | 20 | 20 | 100.00 | |
| tl_d_outstanding_access | 50 | 50 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.910s | 68.745us | 5 | 5 | 100.00 | |
| rv_timer_csr_rw | 0.910s | 14.222us | 20 | 20 | 100.00 | |
| rv_timer_csr_aliasing | 1.140s | 178.547us | 5 | 5 | 100.00 | |
| rv_timer_same_csr_outstanding | 1.190s | 134.155us | 20 | 20 | 100.00 | |
| tl_d_partial_access | 50 | 50 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.910s | 68.745us | 5 | 5 | 100.00 | |
| rv_timer_csr_rw | 0.910s | 14.222us | 20 | 20 | 100.00 | |
| rv_timer_csr_aliasing | 1.140s | 178.547us | 5 | 5 | 100.00 | |
| rv_timer_same_csr_outstanding | 1.190s | 134.155us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 25 | 25 | 100.00 | |||
| rv_timer_sec_cm | 1.220s | 389.174us | 5 | 5 | 100.00 | |
| rv_timer_tl_intg_err | 1.820s | 431.733us | 20 | 20 | 100.00 | |
| sec_cm_bus_integrity | 20 | 20 | 100.00 | |||
| rv_timer_tl_intg_err | 1.820s | 431.733us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| min_value | 2 | 10 | 20.00 | |||
| rv_timer_min | 2.620s | 51.176us | 2 | 10 | 20.00 | |
| max_value | 0 | 10 | 0.00 | |||
| rv_timer_max | 1.350s | 85.878us | 0 | 10 | 0.00 | |
| stress_all_with_rand_reset | 16 | 20 | 80.00 | |||
| rv_timer_stress_all_with_rand_reset | 57.460s | 11565.643us | 16 | 20 | 80.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * | ||||
| rv_timer_min | 53659928239179040194185366320668594042537711501899439691159655654659891155858 | 78 |
UVM_FATAL @ 240724423 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x40aecf04) == 0x1
UVM_INFO @ 240724423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 81393364328240924115125009714298576349532440043633747247378344265658166932325 | 76 |
UVM_FATAL @ 278482330 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x3702d904) == 0x1
UVM_INFO @ 278482330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 47340383070217416179459810814142218577256441065672736476028235293127043179184 | 75 |
UVM_FATAL @ 210539536 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x9d48f04) == 0x1
UVM_INFO @ 210539536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 52594404097386796754976343467814818882985112853532940848529176256546934447467 | 75 |
UVM_FATAL @ 824194529 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x12982104) == 0x1
UVM_INFO @ 824194529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 73955193755247664861686169659703152546745118246820712787355370681296766072757 | 75 |
UVM_FATAL @ 257961548 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xb68dcd04) == 0x1
UVM_INFO @ 257961548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 97624873066739021241296594363860362765176106506902146258987683258197379986431 | 77 |
UVM_FATAL @ 300834469 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x3d13e504) == 0x1
UVM_INFO @ 300834469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 95011266694585731714157984054163512934820083431763320688472594288897033079511 | 77 |
UVM_FATAL @ 117107691 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x46aaf04) == 0x1
UVM_INFO @ 117107691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 66916156527831932305895696047420894727450859269663680245291789932666704407632 | 75 |
UVM_FATAL @ 312068973 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x96a3df04) == 0x1
UVM_INFO @ 312068973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 41465190870211912394693697114348939440685591178585136713409672116926501139905 | 75 |
UVM_FATAL @ 51175696 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x5b770d04) == 0x1
UVM_INFO @ 51175696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 93984644332493728371377358372382947139766942759368532086609018177333591718929 | 75 |
UVM_FATAL @ 240524673 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x95d78b04) == 0x1
UVM_INFO @ 240524673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 17801252294329680296795544202662227153785127831297681119396064647464826079736 | 75 |
UVM_FATAL @ 860534343 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xbdcb1504) == 0x1
UVM_INFO @ 860534343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 62029918931419325991274053047635502976996653726792791916192298772786355051763 | 75 |
UVM_FATAL @ 2687070467 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x5285a904) == 0x1
UVM_INFO @ 2687070467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 98106195774880193099018428615078264117638661173541730012736862949278713813403 | 76 |
UVM_FATAL @ 707347662 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xb46c5f04) == 0x1
UVM_INFO @ 707347662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 87816498964400444265518830729211992593926896799808943276182468936948767344256 | 75 |
UVM_FATAL @ 1584015327 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xa63a0704) == 0x1
UVM_INFO @ 1584015327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 3149626001200326988477382600309241145907955740145811064037929722676806167783 | 76 |
UVM_FATAL @ 191080696 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xe4353504) == 0x1
UVM_INFO @ 191080696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 77879892730661132435921383998914650881416148416627535719298410690706004863303 | 75 |
UVM_FATAL @ 76431373 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x14fb4304) == 0x1
UVM_INFO @ 76431373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 53862953281733079022685385899279058954562556841155607046537514254104685782405 | 75 |
UVM_FATAL @ 191730480 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x850a2504) == 0x1
UVM_INFO @ 191730480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 2358172397883048170503130003447155567936029569922721722050270351345903614286 | 77 |
UVM_FATAL @ 870665337 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xb50cd904) == 0x1
UVM_INFO @ 870665337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 21790149306403116470485311326336448189586757222574361632719314777852092467568 | 75 |
UVM_FATAL @ 512122524 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x8f363b04) == 0x1
UVM_INFO @ 512122524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 72673916707941262311292325132178376737566077804968908623307932208721172061084 | 75 |
UVM_FATAL @ 87914926 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x283e1104) == 0x1
UVM_INFO @ 87914926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 76746313802917188330790658299770843361277525298084627351528372632915498725100 | 75 |
UVM_FATAL @ 66417794 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xe822e304) == 0x1
UVM_INFO @ 66417794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 51276337555805541277510608506286924164158214859990314896384585665955481799725 | 76 |
UVM_FATAL @ 1006895150 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x72e93504) == 0x1
UVM_INFO @ 1006895150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 106655900428455866782095114005888217293778004323124242264616977393817064376414 | 75 |
UVM_FATAL @ 1139648721 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x8ceaed04) == 0x1
UVM_INFO @ 1139648721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 42244381631640533229504689352449987926159913311313426491669077177657344253465 | 75 |
UVM_FATAL @ 251286596 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x2694eb04) == 0x1
UVM_INFO @ 251286596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 56737003842435236567932407266726611961513376305284233970787197974049800566094 | 77 |
UVM_FATAL @ 493848087 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x5159504) == 0x1
UVM_INFO @ 493848087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 89377085053489108130695685913235829497261617851302380422103043969638556367881 | 76 |
UVM_FATAL @ 162193854 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x8ccaa704) == 0x1
UVM_INFO @ 162193854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 42314980480026582076314340950741046350041789205946761142451415677410613778376 | 75 |
UVM_FATAL @ 251926512 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xa8f12f04) == 0x1
UVM_INFO @ 251926512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 98459564573512346059639041917242369270299078668256491717804130129777374488752 | 75 |
UVM_FATAL @ 263506063 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x81574504) == 0x1
UVM_INFO @ 263506063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) | ||||
| rv_timer_max | 39549699935975886811528810836091930973864258057807441555395274522282359441886 | 75 |
UVM_ERROR @ 85878411 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 85878411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 95788748903714476549100713231779077561137350259839278352991202801794583833831 | 75 |
UVM_ERROR @ 48505704 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 48505704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 11632646754412369181308507171365666702217858094206604318700708691596665502365 | 76 |
UVM_ERROR @ 44268188 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 44268188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 29166207435455686279106138518551086354622226007628667383886957623512179886640 | 76 |
UVM_ERROR @ 186379741 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 186379741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 51126960758065862653066157057667520019942264444306981171807552527161205077049 | 75 |
UVM_ERROR @ 89613038 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 89613038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 64382450299537023172461868876009177617816488964668970707814055330790392157312 | 75 |
UVM_ERROR @ 88809898 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 88809898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 34518531210621721600588311477557325807370342805624147743565176954765710287422 | 75 |
UVM_ERROR @ 92845198 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 92845198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 114215056764482854044590660178499282997851342490238205313138024138974974227880 | 75 |
UVM_ERROR @ 168753351 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 168753351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 18779003105932938168771902661461366118965996711479327990543511699887304808775 | 75 |
UVM_ERROR @ 195470639 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 195470639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 71437674791579785424673849613651678370398369068624687004253329593848827389756 | 75 |
UVM_ERROR @ 85289633 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 85289633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (cip_base_vseq.sv:1170) [rv_timer_common_vseq] Check failed (vseq_done) | ||||
| rv_timer_stress_all_with_rand_reset | 71642141836083789100077493617166130406825910206208569130077441363914756294475 | 348 |
UVM_FATAL @ 20887973391 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
UVM_INFO @ 20887973391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| rv_timer_stress_all_with_rand_reset | 29849703205961124378940958479829149060691666935133959081597187353869342517269 | 253 |
UVM_FATAL @ 5173015954 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
UVM_INFO @ 5173015954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues | ||||
| rv_timer_stress_all_with_rand_reset | 18101792355095401395215675004187569335600194772724207131134322671371066715836 | 112 |
UVM_ERROR @ 2588461916 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 2588461916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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|
| rv_timer_stress_all_with_rand_reset | 104225546816529768033418105222031165650037719445227478763870611494052163958192 | 421 |
UVM_ERROR @ 3976424981 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 3976424981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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