Simulation Results

Simulation Results: spi_device/2p

25/04/2026 09:02:00 DVSim: v1.17.3 sha: 8007f61 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
96.09 %

code
94.28 %

assert
94.74 %

func
99.26 %

line
99.16 %

branch
98.49 %

cond
96.65 %

toggle
87.74 %

FSM
89.36 %

Validation stages

V1		100.00%
V2		99.90%
V2S		100.00%
unmapped		98.00%

115/115 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	spi_device_flash_and_tpm	408.150s	266001.942us	50	50	100.00
csr_hw_reset				5	5	100.00
	spi_device_csr_hw_reset	1.180s	43.080us	5	5	100.00
csr_rw				20	20	100.00
	spi_device_csr_rw	2.240s	90.224us	20	20	100.00
csr_bit_bash				5	5	100.00
	spi_device_csr_bit_bash	27.590s	5636.245us	5	5	100.00
csr_aliasing				5	5	100.00
	spi_device_csr_aliasing	14.260s	844.294us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	spi_device_csr_mem_rw_with_rand_reset	3.280s	495.513us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	spi_device_csr_rw	2.240s	90.224us	20	20	100.00
	spi_device_csr_aliasing	14.260s	844.294us	5	5	100.00
mem_walk				5	5	100.00
	spi_device_mem_walk	0.710s	31.176us	5	5	100.00
mem_partial_access				5	5	100.00
	spi_device_mem_partial_access	2.070s	212.060us	5	5	100.00

1040/1041 passed

99.90 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
csb_read				50	50	100.00
	spi_device_csb_read	1.200s	65.379us	50	50	100.00
mem_parity				20	20	100.00
	spi_device_mem_parity	1.490s	32.051us	20	20	100.00
mem_cfg				1	1	100.00
	spi_device_ram_cfg	0.710s	20.532us	1	1	100.00
tpm_read				50	50	100.00
	spi_device_tpm_rw	5.330s	927.100us	50	50	100.00
tpm_write				50	50	100.00
	spi_device_tpm_rw	5.330s	927.100us	50	50	100.00
tpm_hw_reg				100	100	100.00
	spi_device_tpm_read_hw_reg	27.290s	9225.455us	50	50	100.00
	spi_device_tpm_sts_read	1.490s	218.596us	50	50	100.00
tpm_fully_random_case				50	50	100.00
	spi_device_tpm_all	43.720s	9730.181us	50	50	100.00
pass_cmd_filtering				100	100	100.00
	spi_device_pass_cmd_filtering	30.370s	29035.326us	50	50	100.00
	spi_device_flash_all	466.260s	492129.886us	50	50	100.00
pass_addr_translation				100	100	100.00
	spi_device_pass_addr_payload_swap	24.380s	8468.584us	50	50	100.00
	spi_device_flash_all	466.260s	492129.886us	50	50	100.00
pass_payload_translation				100	100	100.00
	spi_device_pass_addr_payload_swap	24.380s	8468.584us	50	50	100.00
	spi_device_flash_all	466.260s	492129.886us	50	50	100.00
cmd_info_slots				50	50	100.00
	spi_device_flash_all	466.260s	492129.886us	50	50	100.00
cmd_read_status				100	100	100.00
	spi_device_intercept	16.740s	1765.765us	50	50	100.00
	spi_device_flash_all	466.260s	492129.886us	50	50	100.00
cmd_read_jedec				100	100	100.00
	spi_device_intercept	16.740s	1765.765us	50	50	100.00
	spi_device_flash_all	466.260s	492129.886us	50	50	100.00
cmd_read_sfdp				100	100	100.00
	spi_device_intercept	16.740s	1765.765us	50	50	100.00
	spi_device_flash_all	466.260s	492129.886us	50	50	100.00
cmd_fast_read				100	100	100.00
	spi_device_intercept	16.740s	1765.765us	50	50	100.00
	spi_device_flash_all	466.260s	492129.886us	50	50	100.00
cmd_read_pipeline				100	100	100.00
	spi_device_intercept	16.740s	1765.765us	50	50	100.00
	spi_device_flash_all	466.260s	492129.886us	50	50	100.00
flash_cmd_upload				50	50	100.00
	spi_device_upload	28.160s	9389.008us	50	50	100.00
mailbox_command				50	50	100.00
	spi_device_mailbox	98.620s	11729.297us	50	50	100.00
mailbox_cross_outside_command				50	50	100.00
	spi_device_mailbox	98.620s	11729.297us	50	50	100.00
mailbox_cross_inside_command				50	50	100.00
	spi_device_mailbox	98.620s	11729.297us	50	50	100.00
cmd_read_buffer				100	100	100.00
	spi_device_flash_mode	51.590s	19548.804us	50	50	100.00
	spi_device_read_buffer_direct	16.500s	7839.518us	50	50	100.00
cmd_dummy_cycle				100	100	100.00
	spi_device_mailbox	98.620s	11729.297us	50	50	100.00
	spi_device_flash_all	466.260s	492129.886us	50	50	100.00
quad_spi				50	50	100.00
	spi_device_flash_all	466.260s	492129.886us	50	50	100.00
dual_spi				50	50	100.00
	spi_device_flash_all	466.260s	492129.886us	50	50	100.00
4b_3b_feature				50	50	100.00
	spi_device_cfg_cmd	19.940s	8546.811us	50	50	100.00
write_enable_disable				50	50	100.00
	spi_device_cfg_cmd	19.940s	8546.811us	50	50	100.00
TPM_with_flash_or_passthrough_mode				50	50	100.00
	spi_device_flash_and_tpm	408.150s	266001.942us	50	50	100.00
tpm_and_flash_trans_with_min_inactive_time				49	50	98.00
	spi_device_flash_and_tpm_min_idle	294.140s	140789.869us	49	50	98.00
stress_all				50	50	100.00
	spi_device_stress_all	567.170s	70176.234us	50	50	100.00
alert_test				50	50	100.00
	spi_device_alert_test	1.150s	18.299us	50	50	100.00
intr_test				50	50	100.00
	spi_device_intr_test	1.110s	16.757us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	spi_device_tl_errors	4.010s	956.201us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	spi_device_tl_errors	4.010s	956.201us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	spi_device_csr_hw_reset	1.180s	43.080us	5	5	100.00
	spi_device_csr_rw	2.240s	90.224us	20	20	100.00
	spi_device_csr_aliasing	14.260s	844.294us	5	5	100.00
	spi_device_same_csr_outstanding	3.570s	780.267us	20	20	100.00
tl_d_partial_access				50	50	100.00
	spi_device_csr_hw_reset	1.180s	43.080us	5	5	100.00
	spi_device_csr_rw	2.240s	90.224us	20	20	100.00
	spi_device_csr_aliasing	14.260s	844.294us	5	5	100.00
	spi_device_same_csr_outstanding	3.570s	780.267us	20	20	100.00

V2S

25/25 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				25	25	100.00
	spi_device_tl_intg_err	17.050s	3443.931us	20	20	100.00
	spi_device_sec_cm	1.340s	67.656us	5	5	100.00
sec_cm_bus_integrity				20	20	100.00
	spi_device_tl_intg_err	17.050s	3443.931us	20	20	100.00

unmapped

49/50 passed

98.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				49	50	98.00
	spi_device_flash_mode_ignore_cmds	317.870s	244094.946us	49	50	98.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (spi_device_scoreboard.sv:2512) [scoreboard] Check failed item.d_data == `gmv(csr) (* [] vs []) CSR last_read_addr compare mismatch act != exp *
	spi_device_flash_and_tpm_min_idle	41776823786362836861802734550676465273545061252602113542603695652700630242333	129	UVM_ERROR @ 17492952784 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (8702976 [0x84cc00] vs 0 [0x0]) CSR last_read_addr compare mismatch act 0x84cc00 != exp 0x0 tl_ul_fuzzy_flash_status_q[i] = 0xa4d53e tl_ul_fuzzy_flash_status_q[i] = 0x841d1a tl_ul_fuzzy_flash_status_q[i] = 0x841d1a UVM_INFO @ 17853392784 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 9/12
	spi_device_flash_mode_ignore_cmds	10516741862024017088117902421841812712928392646910010681886531032832326399195	95	UVM_ERROR @ 1211959708 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (8751104 [0x858800] vs 0 [0x0]) CSR last_read_addr compare mismatch act 0x858800 != exp 0x0 UVM_INFO @ 1330584708 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 4/9 UVM_INFO @ 1330584708 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 5/9 UVM_INFO @ 1670842708 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 5/9 UVM_INFO @ 1670842708 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 6/9