Simulation Results: sram_ctrl/main

 
25/04/2026 09:02:00 DVSim: v1.17.3 sha: 8007f61 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.71 %
  • code
  • 96.88 %
  • assert
  • 96.46 %
  • func
  • 96.80 %
  • block
  • 96.22 %
  • line
  • 96.96 %
  • branch
  • 94.49 %
  • toggle
  • 96.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 5 5 100.00
sram_ctrl_smoke 32.000s 703.599us 5 5 100.00
csr_hw_reset 5 5 100.00
sram_ctrl_csr_hw_reset 2.000s 22.351us 5 5 100.00
csr_rw 20 20 100.00
sram_ctrl_csr_rw 2.000s 17.864us 20 20 100.00
csr_bit_bash 5 5 100.00
sram_ctrl_csr_bit_bash 3.000s 99.923us 5 5 100.00
csr_aliasing 5 5 100.00
sram_ctrl_csr_aliasing 2.000s 16.840us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 5.000s 353.437us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sram_ctrl_csr_rw 2.000s 17.864us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 16.840us 5 5 100.00
mem_walk 5 5 100.00
sram_ctrl_mem_walk 308.000s 82668.349us 5 5 100.00
mem_partial_access 5 5 100.00
sram_ctrl_mem_partial_access 140.000s 21954.592us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 5 5 100.00
sram_ctrl_multiple_keys 73.000s 25750.846us 5 5 100.00
stress_pipeline 5 5 100.00
sram_ctrl_stress_pipeline 232.000s 73374.185us 5 5 100.00
bijection 5 5 100.00
sram_ctrl_bijection 225.000s 67163.111us 5 5 100.00
access_during_key_req 5 5 100.00
sram_ctrl_access_during_key_req 78.000s 59429.528us 5 5 100.00
lc_escalation 5 5 100.00
sram_ctrl_lc_escalation 80.000s 32775.039us 5 5 100.00
executable 5 5 100.00
sram_ctrl_executable 53.000s 72242.799us 5 5 100.00
partial_access 10 10 100.00
sram_ctrl_partial_access 35.000s 2801.270us 5 5 100.00
sram_ctrl_partial_access_b2b 273.000s 79555.804us 5 5 100.00
max_throughput 15 15 100.00
sram_ctrl_max_throughput 36.000s 1339.341us 5 5 100.00
sram_ctrl_throughput_w_partial_write 34.000s 667.545us 5 5 100.00
sram_ctrl_throughput_w_readback 34.000s 1376.825us 5 5 100.00
regwen 5 5 100.00
sram_ctrl_regwen 37.000s 3005.731us 5 5 100.00
ram_cfg 5 5 100.00
sram_ctrl_ram_cfg 31.000s 1059.410us 5 5 100.00
stress_all 5 5 100.00
sram_ctrl_stress_all 502.000s 36136.858us 5 5 100.00
alert_test 50 50 100.00
sram_ctrl_alert_test 30.000s 43.660us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sram_ctrl_tl_errors 6.000s 142.775us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sram_ctrl_tl_errors 6.000s 142.775us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sram_ctrl_csr_hw_reset 2.000s 22.351us 5 5 100.00
sram_ctrl_csr_rw 2.000s 17.864us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 16.840us 5 5 100.00
sram_ctrl_same_csr_outstanding 2.000s 43.016us 20 20 100.00
tl_d_partial_access 50 50 100.00
sram_ctrl_csr_hw_reset 2.000s 22.351us 5 5 100.00
sram_ctrl_csr_rw 2.000s 17.864us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 16.840us 5 5 100.00
sram_ctrl_same_csr_outstanding 2.000s 43.016us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 50.000s 41325.186us 20 20 100.00
tl_intg_err 25 25 100.00
sram_ctrl_sec_cm 31.000s 647.169us 5 5 100.00
sram_ctrl_tl_intg_err 4.000s 900.667us 20 20 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 31.000s 647.169us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
sram_ctrl_tl_intg_err 4.000s 900.667us 20 20 100.00
sec_cm_ctrl_config_regwen 5 5 100.00
sram_ctrl_regwen 37.000s 3005.731us 5 5 100.00
sec_cm_readback_config_regwen 5 5 100.00
sram_ctrl_regwen 37.000s 3005.731us 5 5 100.00
sec_cm_exec_config_regwen 20 20 100.00
sram_ctrl_csr_rw 2.000s 17.864us 20 20 100.00
sec_cm_exec_config_mubi 5 5 100.00
sram_ctrl_executable 53.000s 72242.799us 5 5 100.00
sec_cm_exec_intersig_mubi 5 5 100.00
sram_ctrl_executable 53.000s 72242.799us 5 5 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 5 5 100.00
sram_ctrl_executable 53.000s 72242.799us 5 5 100.00
sec_cm_lc_escalate_en_intersig_mubi 5 5 100.00
sram_ctrl_lc_escalation 80.000s 32775.039us 5 5 100.00
sec_cm_prim_ram_ctrl_mubi 5 5 100.00
sram_ctrl_mubi_enc_err 32.000s 2797.351us 5 5 100.00
sec_cm_mem_integrity 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 50.000s 41325.186us 20 20 100.00
sec_cm_mem_readback 5 5 100.00
sram_ctrl_readback_err 35.000s 2800.869us 5 5 100.00
sec_cm_mem_scramble 5 5 100.00
sram_ctrl_smoke 32.000s 703.599us 5 5 100.00
sec_cm_addr_scramble 5 5 100.00
sram_ctrl_smoke 32.000s 703.599us 5 5 100.00
sec_cm_instr_bus_lc_gated 5 5 100.00
sram_ctrl_executable 53.000s 72242.799us 5 5 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 31.000s 647.169us 5 5 100.00
sec_cm_key_global_esc 5 5 100.00
sram_ctrl_lc_escalation 80.000s 32775.039us 5 5 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 31.000s 647.169us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 31.000s 647.169us 5 5 100.00
sec_cm_scramble_key_sideload 5 5 100.00
sram_ctrl_smoke 32.000s 703.599us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 31.000s 647.169us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 5 100.00
sram_ctrl_stress_all_with_rand_reset 47.000s 5461.519us 5 5 100.00