Simulation Results: sram_ctrl/ret

 
25/04/2026 09:02:00 DVSim: v1.17.3 sha: 8007f61 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.15 %
  • code
  • 83.42 %
  • assert
  • 96.43 %
  • func
  • 96.60 %
  • block
  • 93.87 %
  • line
  • 95.04 %
  • branch
  • 89.67 %
  • toggle
  • 82.28 %
  • FSM
  • 66.67 %
Validation stages
V1
98.57%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 5 5 100.00
sram_ctrl_smoke 3.000s 109.439us 5 5 100.00
csr_hw_reset 5 5 100.00
sram_ctrl_csr_hw_reset 6.000s 47.387us 5 5 100.00
csr_rw 20 20 100.00
sram_ctrl_csr_rw 6.000s 22.983us 20 20 100.00
csr_bit_bash 5 5 100.00
sram_ctrl_csr_bit_bash 7.000s 142.592us 5 5 100.00
csr_aliasing 5 5 100.00
sram_ctrl_csr_aliasing 6.000s 56.172us 5 5 100.00
csr_mem_rw_with_rand_reset 19 20 95.00
sram_ctrl_csr_mem_rw_with_rand_reset 5.000s 31.554us 19 20 95.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sram_ctrl_csr_rw 6.000s 22.983us 20 20 100.00
sram_ctrl_csr_aliasing 6.000s 56.172us 5 5 100.00
mem_walk 5 5 100.00
sram_ctrl_mem_walk 7.000s 683.977us 5 5 100.00
mem_partial_access 5 5 100.00
sram_ctrl_mem_partial_access 6.000s 150.268us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 5 5 100.00
sram_ctrl_multiple_keys 13.000s 2427.988us 5 5 100.00
stress_pipeline 5 5 100.00
sram_ctrl_stress_pipeline 246.000s 3587.460us 5 5 100.00
bijection 5 5 100.00
sram_ctrl_bijection 9.000s 573.464us 5 5 100.00
access_during_key_req 5 5 100.00
sram_ctrl_access_during_key_req 25.000s 2188.788us 5 5 100.00
lc_escalation 5 5 100.00
sram_ctrl_lc_escalation 11.000s 3099.848us 5 5 100.00
executable 5 5 100.00
sram_ctrl_executable 15.000s 1896.984us 5 5 100.00
partial_access 10 10 100.00
sram_ctrl_partial_access 3.000s 127.782us 5 5 100.00
sram_ctrl_partial_access_b2b 259.000s 84297.067us 5 5 100.00
max_throughput 15 15 100.00
sram_ctrl_max_throughput 2.000s 149.586us 5 5 100.00
sram_ctrl_throughput_w_partial_write 2.000s 65.938us 5 5 100.00
sram_ctrl_throughput_w_readback 3.000s 78.092us 5 5 100.00
regwen 5 5 100.00
sram_ctrl_regwen 13.000s 1841.141us 5 5 100.00
ram_cfg 5 5 100.00
sram_ctrl_ram_cfg 2.000s 83.515us 5 5 100.00
stress_all 5 5 100.00
sram_ctrl_stress_all 49.000s 733.492us 5 5 100.00
alert_test 50 50 100.00
sram_ctrl_alert_test 2.000s 17.560us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sram_ctrl_tl_errors 8.000s 361.135us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sram_ctrl_tl_errors 8.000s 361.135us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sram_ctrl_csr_hw_reset 6.000s 47.387us 5 5 100.00
sram_ctrl_csr_rw 6.000s 22.983us 20 20 100.00
sram_ctrl_csr_aliasing 6.000s 56.172us 5 5 100.00
sram_ctrl_same_csr_outstanding 5.000s 13.691us 20 20 100.00
tl_d_partial_access 50 50 100.00
sram_ctrl_csr_hw_reset 6.000s 47.387us 5 5 100.00
sram_ctrl_csr_rw 6.000s 22.983us 20 20 100.00
sram_ctrl_csr_aliasing 6.000s 56.172us 5 5 100.00
sram_ctrl_same_csr_outstanding 5.000s 13.691us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 8.000s 3357.833us 20 20 100.00
tl_intg_err 25 25 100.00
sram_ctrl_sec_cm 8.000s 2365.166us 5 5 100.00
sram_ctrl_tl_intg_err 6.000s 351.004us 20 20 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 8.000s 2365.166us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
sram_ctrl_tl_intg_err 6.000s 351.004us 20 20 100.00
sec_cm_ctrl_config_regwen 5 5 100.00
sram_ctrl_regwen 13.000s 1841.141us 5 5 100.00
sec_cm_readback_config_regwen 5 5 100.00
sram_ctrl_regwen 13.000s 1841.141us 5 5 100.00
sec_cm_exec_config_regwen 20 20 100.00
sram_ctrl_csr_rw 6.000s 22.983us 20 20 100.00
sec_cm_exec_config_mubi 5 5 100.00
sram_ctrl_executable 15.000s 1896.984us 5 5 100.00
sec_cm_exec_intersig_mubi 5 5 100.00
sram_ctrl_executable 15.000s 1896.984us 5 5 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 5 5 100.00
sram_ctrl_executable 15.000s 1896.984us 5 5 100.00
sec_cm_lc_escalate_en_intersig_mubi 5 5 100.00
sram_ctrl_lc_escalation 11.000s 3099.848us 5 5 100.00
sec_cm_prim_ram_ctrl_mubi 5 5 100.00
sram_ctrl_mubi_enc_err 2.000s 84.780us 5 5 100.00
sec_cm_mem_integrity 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 8.000s 3357.833us 20 20 100.00
sec_cm_mem_readback 5 5 100.00
sram_ctrl_readback_err 3.000s 266.863us 5 5 100.00
sec_cm_mem_scramble 5 5 100.00
sram_ctrl_smoke 3.000s 109.439us 5 5 100.00
sec_cm_addr_scramble 5 5 100.00
sram_ctrl_smoke 3.000s 109.439us 5 5 100.00
sec_cm_instr_bus_lc_gated 5 5 100.00
sram_ctrl_executable 15.000s 1896.984us 5 5 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 8.000s 2365.166us 5 5 100.00
sec_cm_key_global_esc 5 5 100.00
sram_ctrl_lc_escalation 11.000s 3099.848us 5 5 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 8.000s 2365.166us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 8.000s 2365.166us 5 5 100.00
sec_cm_scramble_key_sideload 5 5 100.00
sram_ctrl_smoke 3.000s 109.439us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 8.000s 2365.166us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 5 100.00
sram_ctrl_stress_all_with_rand_reset 32.000s 5055.387us 5 5 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: *
sram_ctrl_csr_mem_rw_with_rand_reset 32732674737962597917508812126458593360109906716175261304692133330852017804460 88
UVM_ERROR @ 24212287 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: 0x0
UVM_INFO @ 24212287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---