Simulation Results: sysrst_ctrl

 
25/04/2026 09:02:00 DVSim: v1.17.3 sha: 8007f61 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.73 %
  • code
  • 98.25 %
  • assert
  • 98.18 %
  • func
  • 84.75 %
  • line
  • 99.09 %
  • branch
  • 99.22 %
  • cond
  • 98.06 %
  • toggle
  • 100.00 %
  • FSM
  • 94.87 %
Validation stages
V1
100.00%
V2
98.06%
V2S
100.00%
V3
96.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
sysrst_ctrl_smoke 8.670s 2110.896us 50 50 100.00
input_output_inverted 50 50 100.00
sysrst_ctrl_in_out_inverted 10.490s 2466.125us 50 50 100.00
combo_detect_ec_rst 5 5 100.00
sysrst_ctrl_combo_detect_ec_rst 5.920s 2198.425us 5 5 100.00
combo_detect_ec_rst_with_pre_cond 5 5 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 7.980s 2269.140us 5 5 100.00
csr_hw_reset 5 5 100.00
sysrst_ctrl_csr_hw_reset 20.320s 6033.043us 5 5 100.00
csr_rw 20 20 100.00
sysrst_ctrl_csr_rw 8.570s 2056.359us 20 20 100.00
csr_bit_bash 5 5 100.00
sysrst_ctrl_csr_bit_bash 130.110s 75832.945us 5 5 100.00
csr_aliasing 5 5 100.00
sysrst_ctrl_csr_aliasing 12.410s 2863.701us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 9.260s 2050.269us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sysrst_ctrl_csr_rw 8.570s 2056.359us 20 20 100.00
sysrst_ctrl_csr_aliasing 12.410s 2863.701us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 50 50 100.00
sysrst_ctrl_combo_detect 512.060s 195636.970us 50 50 100.00
combo_detect_with_pre_cond 94 100 94.00
sysrst_ctrl_combo_detect_with_pre_cond 440.700s 257672.395us 94 100 94.00
auto_block_key_outputs 50 50 100.00
sysrst_ctrl_auto_blk_key_output 1050.670s 508491.901us 50 50 100.00
keyboard_input_triggered_interrupt 49 50 98.00
sysrst_ctrl_edge_detect 311.040s 677162.597us 49 50 98.00
pin_output_keyboard_inversion_control 50 50 100.00
sysrst_ctrl_pin_override_test 10.260s 2512.538us 50 50 100.00
pin_input_value_accessibility 50 50 100.00
sysrst_ctrl_pin_access_test 9.950s 2170.803us 50 50 100.00
ec_power_on_reset 50 50 100.00
sysrst_ctrl_ec_pwr_on_rst 443.740s 1705385.762us 50 50 100.00
flash_write_protect_output 50 50 100.00
sysrst_ctrl_flash_wr_prot_out 11.530s 2610.150us 50 50 100.00
ultra_low_power_test 44 50 88.00
sysrst_ctrl_ultra_low_pwr 453.340s 2343987.968us 44 50 88.00
sysrst_ctrl_feature_disable 2 2 100.00
sysrst_ctrl_feature_disable 66.470s 36758.803us 2 2 100.00
stress_all 49 50 98.00
sysrst_ctrl_stress_all 658.840s 295122.541us 49 50 98.00
alert_test 50 50 100.00
sysrst_ctrl_alert_test 8.620s 2011.305us 50 50 100.00
intr_test 50 50 100.00
sysrst_ctrl_intr_test 8.030s 2016.550us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sysrst_ctrl_tl_errors 10.170s 2167.108us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sysrst_ctrl_tl_errors 10.170s 2167.108us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sysrst_ctrl_csr_hw_reset 20.320s 6033.043us 5 5 100.00
sysrst_ctrl_csr_rw 8.570s 2056.359us 20 20 100.00
sysrst_ctrl_csr_aliasing 12.410s 2863.701us 5 5 100.00
sysrst_ctrl_same_csr_outstanding 22.460s 9795.743us 20 20 100.00
tl_d_partial_access 50 50 100.00
sysrst_ctrl_csr_hw_reset 20.320s 6033.043us 5 5 100.00
sysrst_ctrl_csr_rw 8.570s 2056.359us 20 20 100.00
sysrst_ctrl_csr_aliasing 12.410s 2863.701us 5 5 100.00
sysrst_ctrl_same_csr_outstanding 22.460s 9795.743us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
sysrst_ctrl_tl_intg_err 112.060s 42403.302us 20 20 100.00
sysrst_ctrl_sec_cm 71.930s 22012.483us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
sysrst_ctrl_tl_intg_err 112.060s 42403.302us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 48 50 96.00
sysrst_ctrl_stress_all_with_rand_reset 19.100s 5939.523us 48 50 96.00

Error Messages

   Test seed line log context
UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) 
sysrst_ctrl_ultra_low_pwr 19524834702708759575347433064761914974582523199360177569676196252762203170049 658
UVM_ERROR @ 4300278267 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) 
UVM_ERROR @ 6107778267 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 6107778267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sysrst_ctrl_stress_all_with_rand_reset 89460484633159536326941300161729173544465637006396093265995832773458576761233 695
UVM_ERROR @ 20256708399 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) 
UVM_INFO @ 20269208399 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i
UVM_INFO @ 172054208399 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
UVM_INFO @ 172143477163 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_smoke_vseq
UVM_INFO @ 174139477163 ps: (sysrst_ctrl_smoke_vseq.sv:14) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_smoke_vseq] Starting the body from smoke_seq
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error
sysrst_ctrl_ultra_low_pwr 86084998649638887155240852582611297955220615583587075951407477812427714625900 659
UVM_ERROR @ 550432252704 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 550432273538 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 550432273538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sysrst_ctrl_ultra_low_pwr 10610091860860151198478999409794761370250730283015842684879303615014848554262 658
UVM_ERROR @ 4183279965 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 4183363299 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 4183363299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sysrst_ctrl_edge_detect 22915673057745138133600436001262705693269610219041099950173904354787022910486 669
UVM_ERROR @ 2705189865 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 2705210483 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 2705210483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sysrst_ctrl_ultra_low_pwr 113041922443036151819812649079767508394131418905177589494038553181749263467410 659
UVM_ERROR @ 6559982621 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 6560023437 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 6560023437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sysrst_ctrl_ultra_low_pwr 111656224758340077665533729009320889649404171671988429469795415278605194998790 659
UVM_ERROR @ 4352097895 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 4352137895 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 4352137895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sysrst_ctrl_ultra_low_pwr 37891214147630439532926901017171410059363719797918488424890190472862758392180 659
UVM_ERROR @ 3031058408 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 3031225074 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 3031225074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sysrst_ctrl_stress_all_with_rand_reset 80227934756478622413041504993905577575901082037261661917808845131848602432697 713
UVM_ERROR @ 13224397483 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 13224461999 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 13224461999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sysrst_ctrl_stress_all 13090204165986740200866942417514352606518182502683324083715049744125636657468 659
UVM_ERROR @ 4316879882 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 4316900716 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 4316900716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*])
sysrst_ctrl_combo_detect_with_pre_cond 72717825547940230925290114018990372746485348230418133423874013318780439463808 669
UVM_ERROR @ 15150284829 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
UVM_ERROR @ 15150284829 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 15150284829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sysrst_ctrl_combo_detect_with_pre_cond 13341487425915347490496843554584582161304080309848398598419874519984956428245 697
UVM_ERROR @ 36388727765 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
UVM_ERROR @ 36388727765 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 36388727765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sysrst_ctrl_combo_detect_with_pre_cond 9044985632275646260685967193517921731531763289735875490636142916201448265910 686
UVM_ERROR @ 64668664498 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
UVM_ERROR @ 64668664498 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 64668664498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sysrst_ctrl_combo_detect_with_pre_cond 66012393934830140339179589201423133403561697292821257307803987574673096096898 727
UVM_ERROR @ 66794863353 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
UVM_ERROR @ 66794863353 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 66794863353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sysrst_ctrl_combo_detect_with_pre_cond 61991839303983090486030578982770110289402949584549743921106652926787776836193 725
UVM_ERROR @ 105805214180 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
UVM_ERROR @ 105805214180 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 105805214180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [*] vs * [*])
sysrst_ctrl_combo_detect_with_pre_cond 7795252951567760720319687892534691012114613535910987016847145442119655366207 752
UVM_ERROR @ 144281574271 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 145081574271 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
UVM_INFO @ 145101574271 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
UVM_INFO @ 155512012014 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0xe9
UVM_INFO @ 155512032632 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x32