Simulation Results

Simulation Results: csrng

02/05/2026 09:12:14 DVSim: v1.17.3 sha: 63c8a50 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
94.19 %

code
96.23 %

assert
95.85 %

func
90.50 %

block
98.59 %

line
99.57 %

branch
96.46 %

toggle
93.64 %

FSM
95.24 %

Validation stages

V1		100.00%
V2		96.73%
V2S		99.70%
V3		0.00%

105/105 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	csrng_smoke	6.000s	252.657us	50	50	100.00
csr_hw_reset				5	5	100.00
	csrng_csr_hw_reset	3.000s	102.938us	5	5	100.00
csr_rw				20	20	100.00
	csrng_csr_rw	3.000s	33.803us	20	20	100.00
csr_bit_bash				5	5	100.00
	csrng_csr_bit_bash	28.000s	1840.173us	5	5	100.00
csr_aliasing				5	5	100.00
	csrng_csr_aliasing	6.000s	267.659us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	csrng_csr_mem_rw_with_rand_reset	4.000s	165.020us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	csrng_csr_rw	3.000s	33.803us	20	20	100.00
	csrng_csr_aliasing	6.000s	267.659us	5	5	100.00

1422/1470 passed

96.73 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
interrupts				200	200	100.00
	csrng_intr	21.000s	1276.080us	200	200	100.00
alerts				500	500	100.00
	csrng_alert	40.000s	3609.114us	500	500	100.00
err				498	500	99.60
	csrng_err	4.000s	115.310us	498	500	99.60
cmds				6	50	12.00
	csrng_cmds	84.000s	2311.469us	6	50	12.00
life cycle				6	50	12.00
	csrng_cmds	84.000s	2311.469us	6	50	12.00
stress_all				48	50	96.00
	csrng_stress_all	930.000s	59799.651us	48	50	96.00
intr_test				50	50	100.00
	csrng_intr_test	4.000s	143.657us	50	50	100.00
alert_test				50	50	100.00
	csrng_alert_test	4.000s	107.620us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	csrng_tl_errors	9.000s	494.645us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	csrng_tl_errors	9.000s	494.645us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	csrng_csr_hw_reset	3.000s	102.938us	5	5	100.00
	csrng_csr_rw	3.000s	33.803us	20	20	100.00
	csrng_csr_aliasing	6.000s	267.659us	5	5	100.00
	csrng_same_csr_outstanding	6.000s	221.544us	20	20	100.00
tl_d_partial_access				50	50	100.00
	csrng_csr_hw_reset	3.000s	102.938us	5	5	100.00
	csrng_csr_rw	3.000s	33.803us	20	20	100.00
	csrng_csr_aliasing	6.000s	267.659us	5	5	100.00
	csrng_same_csr_outstanding	6.000s	221.544us	20	20	100.00

V2S

1341/1345 passed

99.70 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				25	25	100.00
	csrng_sec_cm	7.000s	289.528us	5	5	100.00
	csrng_tl_intg_err	23.000s	707.066us	20	20	100.00
sec_cm_config_regwen				70	70	100.00
	csrng_regwen	3.000s	25.158us	50	50	100.00
	csrng_csr_rw	3.000s	33.803us	20	20	100.00
sec_cm_config_mubi				500	500	100.00
	csrng_alert	40.000s	3609.114us	500	500	100.00
sec_cm_intersig_mubi				48	50	96.00
	csrng_stress_all	930.000s	59799.651us	48	50	96.00
sec_cm_main_sm_fsm_sparse				703	705	99.72
	csrng_intr	21.000s	1276.080us	200	200	100.00
	csrng_err	4.000s	115.310us	498	500	99.60
	csrng_sec_cm	7.000s	289.528us	5	5	100.00
sec_cm_cmd_stage_fsm_sparse				703	705	99.72
	csrng_intr	21.000s	1276.080us	200	200	100.00
	csrng_err	4.000s	115.310us	498	500	99.60
	csrng_sec_cm	7.000s	289.528us	5	5	100.00
sec_cm_ctr_drbg_fsm_sparse				703	705	99.72
	csrng_intr	21.000s	1276.080us	200	200	100.00
	csrng_err	4.000s	115.310us	498	500	99.60
	csrng_sec_cm	7.000s	289.528us	5	5	100.00
sec_cm_ctr_drbg_ctr_redun				703	705	99.72
	csrng_intr	21.000s	1276.080us	200	200	100.00
	csrng_err	4.000s	115.310us	498	500	99.60
	csrng_sec_cm	7.000s	289.528us	5	5	100.00
sec_cm_gen_cmd_ctr_redun				703	705	99.72
	csrng_intr	21.000s	1276.080us	200	200	100.00
	csrng_err	4.000s	115.310us	498	500	99.60
	csrng_sec_cm	7.000s	289.528us	5	5	100.00
sec_cm_ctrl_mubi				500	500	100.00
	csrng_alert	40.000s	3609.114us	500	500	100.00
sec_cm_main_sm_ctr_local_esc				698	700	99.71
	csrng_intr	21.000s	1276.080us	200	200	100.00
	csrng_err	4.000s	115.310us	498	500	99.60
sec_cm_constants_lc_gated				48	50	96.00
	csrng_stress_all	930.000s	59799.651us	48	50	96.00
sec_cm_sw_genbits_bus_consistency				500	500	100.00
	csrng_alert	40.000s	3609.114us	500	500	100.00
sec_cm_tile_link_bus_integrity				20	20	100.00
	csrng_tl_intg_err	23.000s	707.066us	20	20	100.00
sec_cm_aes_cipher_fsm_sparse				703	705	99.72
	csrng_intr	21.000s	1276.080us	200	200	100.00
	csrng_err	4.000s	115.310us	498	500	99.60
	csrng_sec_cm	7.000s	289.528us	5	5	100.00
sec_cm_aes_cipher_fsm_redun				698	700	99.71
	csrng_intr	21.000s	1276.080us	200	200	100.00
	csrng_err	4.000s	115.310us	498	500	99.60
sec_cm_aes_cipher_ctrl_sparse				698	700	99.71
	csrng_intr	21.000s	1276.080us	200	200	100.00
	csrng_err	4.000s	115.310us	498	500	99.60
sec_cm_aes_cipher_fsm_local_esc				698	700	99.71
	csrng_intr	21.000s	1276.080us	200	200	100.00
	csrng_err	4.000s	115.310us	498	500	99.60
sec_cm_aes_cipher_ctr_redun				703	705	99.72
	csrng_intr	21.000s	1276.080us	200	200	100.00
	csrng_err	4.000s	115.310us	498	500	99.60
	csrng_sec_cm	7.000s	289.528us	5	5	100.00
sec_cm_aes_cipher_data_reg_local_esc				698	700	99.71
	csrng_intr	21.000s	1276.080us	200	200	100.00
	csrng_err	4.000s	115.310us	498	500	99.60

0/10 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	10	0.00
	csrng_stress_all_with_rand_reset	0.000s	0.000us	0	10	0.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (csrng_scoreboard.sv:660) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [] vs [*])
	csrng_cmds	75840417044028364890839669456483585989413821646518721933443118250007758263419	130	UVM_FATAL @ 81094867 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 57266435610902444873475839149195107682 [0x2b151d43c1bacd4d0a99d96829839d62]) UVM_INFO @ 81094867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	18130458492160706173330827177517498988471748894669908948086003612436690013457	140	UVM_FATAL @ 40897776 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 228113109327249521910401557218735246163 [0xab9cfc9eaab207bfbdc3ffcdfdcd4b53]) UVM_INFO @ 40897776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	71093417501085915492986747051594053691506615345473463650229747647227427736913	130	UVM_FATAL @ 61738838 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 263534255963497883793578413419736809903 [0xc642d9fb753090e57a0acf05405f41af]) UVM_INFO @ 61738838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	44463928932666425419693800869885044360374493413482837165874471979337646000826	130	UVM_FATAL @ 1082716423 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 287787171320283300460544605619263147821 [0xd881cb07a8cf0f070e38b798450c8f2d]) UVM_INFO @ 1082716423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	112179233911261938248443934256823659238075423403042529120254514818776567440128	130	UVM_FATAL @ 18139682 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 115615469009914702822310569354446436915 [0x56fabab8a6c2d4faf142b88ce1befa33]) UVM_INFO @ 18139682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	6018655663299194161132717217883111705410565538104574578068233439038878310161	130	UVM_FATAL @ 61862181 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 215024630924566982470094564150682379225 [0xa1c43ccfef7c039a69ac87823340e3d9]) UVM_INFO @ 61862181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	19353009810375062889215795566811659508902422282329103882335383346509790749618	150	UVM_FATAL @ 2073382196 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 296451315146665621851642186977433342788 [0xdf06724d210185370432e63811d7d344]) UVM_INFO @ 2073382196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	2400774716895387632231825373657392599880594479635012262732674610357870970210	130	UVM_FATAL @ 65402038 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 224413847234528646414824298568280676888 [0xa8d488eac6e6fb3e35da8ffa92b39a18]) UVM_INFO @ 65402038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	30443180213148893148569332564499603490074005916141074216678110837852297262060	130	UVM_FATAL @ 203266860 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 283295996911791255878191153379306756126 [0xd520d3091bf420a58c87bece4089d81e]) UVM_INFO @ 203266860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	74125825881105130689299273297186394544203628793500611945088390371757966813894	130	UVM_FATAL @ 25421086 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 113475671088922671953734740803899829676 [0x555e9e89da30f2e0e573ceac4d132dac]) UVM_INFO @ 25421086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	83715956062597452733811355082365919086694515204575744805592094830564517768762	130	UVM_FATAL @ 691109237 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 151300318188395306482254172798196794361 [0x71d3619f7610d2f77e56201ac49e43f9]) UVM_INFO @ 691109237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	60166168083053872832048618684593230014196270762018774758951627800447925746831	130	UVM_FATAL @ 93229902 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 262171328255528706617640766193586971237 [0xc53c5c754a5920c50b41dd1ad618a265]) UVM_INFO @ 93229902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	101804698059770646084562750837648822662563320606106425145627167799461948546142	130	UVM_FATAL @ 17820150 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 105770106435447786237413015859772672137 [0x4f9294de8720a2648d6050a0ce2e4889]) UVM_INFO @ 17820150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	45904970200752881217146661445491356249217725981904099047035549400447634204687	130	UVM_FATAL @ 17378277 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 156268700746416985421672751542888898413 [0x759041cba80ef99c0abda81f4d111f6d]) UVM_INFO @ 17378277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	52151389115816980096729536914468578789662892481547533749419167288079414285968	130	UVM_FATAL @ 331748180 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 173569338896649807176222410409328709469 [0x82943d1ccf5ad7154b9ce1464a830f5d]) UVM_INFO @ 331748180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	51660812853390831679868665596817403805099427977262633039798926562229734929249	130	UVM_FATAL @ 23214716 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 102492069939092142308998056177273242025 [0x4d1b41311f3dfdfc476c7f3d1d5181a9]) UVM_INFO @ 23214716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	93176865990059806246199457842067148347130951450322536893662499394526546241170	130	UVM_FATAL @ 49897979 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 215882421684186137568076380924664839611 [0xa2697129751c1d1bc6e3c20d7dc37dbb]) UVM_INFO @ 49897979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	83667477761146142998748158101823085278423373897678348320154208409463337758855	130	UVM_FATAL @ 68558984 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 190965857100742104754716000252454770567 [0x8faaafae6179cdc5aafd34429e301787]) UVM_INFO @ 68558984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	60857007071716175957805638128018655263998091976394680482072258076745766983396	130	UVM_FATAL @ 38279048 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 208545669903535579912143332426151838132 [0x9ce46f5f0a5811a28ff48484f0b341b4]) UVM_INFO @ 38279048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	47632158747027170632265309371058711505383947035437492103507008184251437849285	130	UVM_FATAL @ 10414405 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 203615384134874376227209553595334736920 [0x992ee583edd16b661d6a310dfe013c18]) UVM_INFO @ 10414405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	52014099434966173611770428576452938102659680815215374392266476126734331555219	130	UVM_FATAL @ 82247828 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 185833875544018147624266449705024776031 [0x8bce4d7484a40a575a5205043e22675f]) UVM_INFO @ 82247828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	92453375728218457129569546970355856866279583683197961453915151442102476065283	140	UVM_FATAL @ 2940585641 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 52605057321707017043785885028618752592 [0x27935d923544be685ef57042be8a5250]) UVM_INFO @ 2940585641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	70145844752641737431159552717840844484790590879717678009589891274377223358927	150	UVM_FATAL @ 1079878614 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 158776707077759852187210252537661413019 [0x7773480df9560a0cf4d41a4ebdfad69b]) UVM_INFO @ 1079878614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	22700619902966260435349449030937974978965766550730263090559070900593861224238	130	UVM_FATAL @ 49742033 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 12677957815089682187803546063099815413 [0x989af94742f53e2cf4146a8410665f5]) UVM_INFO @ 49742033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	95134593436130217936826364643553577217251115652941285414171039724060508450439	130	UVM_FATAL @ 114223143 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 297756018320821054514216149398159672336 [0xe001b9225c6f4a6bbd8606f66140c410]) UVM_INFO @ 114223143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	99923887759531851583046211731600894539788048369205840720562691224554161249437	130	UVM_FATAL @ 145944178 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 314390649639985783607701374617539630543 [0xec856fc77d03c0085d4b04bd4768d5cf]) UVM_INFO @ 145944178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	75772862101423697848226924266455229142936451110879245768341138605030372207034	130	UVM_FATAL @ 37697864 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 6541408152894481337468412656660006421 [0x4ebd45282b6a05ac9fa3bf4fbc84615]) UVM_INFO @ 37697864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	82430339935136885733382151331862502381187695009613975918343309586657975775834	130	UVM_FATAL @ 1523684970 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 269287052663809592083004352854706101075 [0xca96ccc20f0970f4fec9cd01aef01b53]) UVM_INFO @ 1523684970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	88673047447018898190493799228808006206592172416933479708448819032767841753917	130	UVM_FATAL @ 56814931 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 60218655800476338070662544158571523772 [0x2d4db0f5371df34e988e8990b4426ebc]) UVM_INFO @ 56814931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	76656572015180427561718950991707693921768709904877254301924450168890142550358	130	UVM_FATAL @ 246755795 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 152421451465695147647827444869284492417 [0x72ab4dc2da6f4a46b43fc9c6a387f481]) UVM_INFO @ 246755795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	106349354171322573342061236003837244398298395438795037957329979310318432292327	130	UVM_FATAL @ 19718497 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 41712391980624936316120741468886291403 [0x1f6183b4bf9155888c29517ad31053cb]) UVM_INFO @ 19718497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	40690455847994319674990577075867340622587975154642881186123361992993562957422	130	UVM_FATAL @ 23997722 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 241815463306880525265054515110739768962 [0xb5ebf6d47dc39ec0324dc32ca72cf682]) UVM_INFO @ 23997722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	12360693803531419095298431413857371889621352489487868077781045414311033507184	130	UVM_FATAL @ 13164286 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 81761749624763089296491770551717492292 [0x3d82bd7d24a2d016c92a3015a25e7644]) UVM_INFO @ 13164286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	40253404580663250755267071990110944086307641002592222603281930438068148652468	140	UVM_FATAL @ 636563516 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 301546745351543047627901820505260814314 [0xe2dbca68124d3a8deb0559b26387efea]) UVM_INFO @ 636563516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	38259425987460445901514579487270636196708279665032142344141179521490236044473	130	UVM_FATAL @ 66678546 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 280139895703049581147563023996174066890 [0xd2c0fb3b67bdd68481341d337485e4ca]) UVM_INFO @ 66678546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	17694639990665910552929064945538230211694571462767940001063695975107012059510	130	UVM_FATAL @ 289410818 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 329335120638955537442513749785929407683 [0xf7c3a316368c822e8f4550aa21095cc3]) UVM_INFO @ 289410818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	27260252030199998654514194251933988413487153936469699826369533835285432934363	130	UVM_FATAL @ 148446744 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 255531897330448152187538710997329102201 [0xc03da73d747d7ad3f8235c58c571c579]) UVM_INFO @ 148446744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	68388542654350977179924784795050967671990757324286618391565622493954553269728	130	UVM_FATAL @ 81709611 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 256952781902503152717032075845278717626 [0xc14f4e42173514ebd7ecc5cdbcc956ba]) UVM_INFO @ 81709611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	92901024474244264494798159797372441059997850386684497052594779555669134213086	130	UVM_FATAL @ 153377894 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 298610361061667640991314907890187160774 [0xe0a6437bc48700b00b988a9e52aeccc6]) UVM_INFO @ 153377894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	83454602783748992332635548359988196392390860845752539066834848202257896152303	130	UVM_FATAL @ 96139617 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 123995052318008564325871335433636379957 [0x5d4894136ea309d09ac2b0300c8f7d35]) UVM_INFO @ 96139617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes
	csrng_stress_all_with_rand_reset	43800326936900584062160093425084696531712917567642228758841468120010796828581	None	Job timed out after 180 minutes
	csrng_stress_all_with_rand_reset	97837160614028901312210946512220573060740584715036889512120991279049377890770	None	Job timed out after 180 minutes
	csrng_stress_all_with_rand_reset	5290651328500583136050146066967255672105879726213123419812932582130512228052	None	Job timed out after 180 minutes
	csrng_stress_all_with_rand_reset	20081733041081318269259204305893169353060038836610853731504150871481578987244	None	Job timed out after 180 minutes
	csrng_stress_all_with_rand_reset	110490463248378678480722489258574283492417218490043647571921700478801174348221	None	Job timed out after 180 minutes
	csrng_stress_all_with_rand_reset	39121614901646562471981072123202897088253574195092442717724113080374638244610	None	Job timed out after 180 minutes
	csrng_stress_all_with_rand_reset	79553287202136500741546954938724028181944129212362680699469918407090655214871	None	Job timed out after 180 minutes
	csrng_stress_all_with_rand_reset	61850809807408065589792786401215807012838732521703713129929750343441992758984	None	Job timed out after 180 minutes
	csrng_stress_all_with_rand_reset	17802828694234790539574663604111884870939305596096629910944357288833255499830	None	Job timed out after 180 minutes
	csrng_stress_all_with_rand_reset	30181863004005047430017703514410564135957825559898089669052193465083870243034	None	Job timed out after 180 minutes
UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [] vs [*]) Interrupt_pin: EntropyReq
	csrng_stress_all	115016157728356937346939574338017084237165551258645751282864587932345565476907	133	UVM_ERROR @ 69594265 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq UVM_INFO @ 69594265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all	26257571906800746187231888530417215969651179222137029822880832120641064006799	145	UVM_ERROR @ 15578153885 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq UVM_INFO @ 15578153885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:418) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: csrng_reg_block.genbits
	csrng_cmds	63110468800574431962088638542035145433229049026458351392604303541240514862035	133	UVM_ERROR @ 165174684 ps: (csrng_scoreboard.sv:418) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1035850835 [0x3dbdd453] vs 0 [0x0]) reg name: csrng_reg_block.genbits UVM_INFO @ 165174684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:268) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [] vs [*]) alert recov_alert triggered unexpectedly
	csrng_cmds	1560811628948112166910403681205835971268847914771398223105512880321964874007	138	UVM_ERROR @ 37088301 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_alert triggered unexpectedly UVM_INFO @ 37088301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csrng_scoreboard.sv:629) [scoreboard] Check failed cs_item[app].status == cmd_sts[app] (* [] vs [*])
	csrng_cmds	1137902134481197798449935691947653085207075280231941808371791179465298802909	149	UVM_FATAL @ 194911445 ps: (csrng_scoreboard.sv:629) [uvm_test_top.env.scoreboard] Check failed cs_item[app].status == cmd_sts[app] (0 [0x0] vs 3 [0x3]) UVM_INFO @ 194911445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	30091480700081173598075882299116501198045111337994531831689050640698972126444	149	UVM_FATAL @ 42358601 ps: (csrng_scoreboard.sv:629) [uvm_test_top.env.scoreboard] Check failed cs_item[app].status == cmd_sts[app] (0 [0x0] vs 3 [0x3]) UVM_INFO @ 42358601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (alert_receiver_driver.sv:219) [driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
	csrng_err	64760417771391360168574462984363083847432236103677035843318990468937696064021	135	UVM_FATAL @ 19511718 ps: (alert_receiver_driver.sv:219) [uvm_test_top.env.m_alert_agent_fatal_alert.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q UVM_INFO @ 19511718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_err	44371927796913343154343089537582502455805406385189151837245204659941117076258	135	UVM_FATAL @ 21841528 ps: (alert_receiver_driver.sv:219) [uvm_test_top.env.m_alert_agent_fatal_alert.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q UVM_INFO @ 21841528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---