Simulation Results

Simulation Results: flash_ctrl

02/05/2026 09:12:14 DVSim: v1.17.3 sha: 63c8a50 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
97.04 %

code
95.90 %

assert
96.76 %

func
98.45 %

line
96.10 %

branch
97.42 %

cond
94.81 %

toggle
98.66 %

FSM
92.52 %

Validation stages

V1		100.00%
V2		99.23%
V2S		99.18%
V3		100.00%
unmapped		100.00%

120/120 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	flash_ctrl_smoke	156.240s	1456.498us	50	50	100.00
smoke_hw				5	5	100.00
	flash_ctrl_smoke_hw	22.590s	29.952us	5	5	100.00
csr_hw_reset				5	5	100.00
	flash_ctrl_csr_hw_reset	19.880s	153.507us	5	5	100.00
csr_rw				20	20	100.00
	flash_ctrl_csr_rw	13.830s	29.856us	20	20	100.00
csr_bit_bash				5	5	100.00
	flash_ctrl_csr_bit_bash	77.990s	7629.847us	5	5	100.00
csr_aliasing				5	5	100.00
	flash_ctrl_csr_aliasing	54.840s	8830.915us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	flash_ctrl_csr_mem_rw_with_rand_reset	16.680s	248.998us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	flash_ctrl_csr_rw	13.830s	29.856us	20	20	100.00
	flash_ctrl_csr_aliasing	54.840s	8830.915us	5	5	100.00
mem_walk				5	5	100.00
	flash_ctrl_mem_walk	9.950s	52.435us	5	5	100.00
mem_partial_access				5	5	100.00
	flash_ctrl_mem_partial_access	12.530s	34.536us	5	5	100.00

1035/1043 passed

99.23 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
sw_op				5	5	100.00
	flash_ctrl_sw_op	24.090s	42.358us	5	5	100.00
host_read_direct				5	5	100.00
	flash_ctrl_host_dir_rd	63.380s	70.534us	5	5	100.00
rma_hw_if				43	43	100.00
	flash_ctrl_hw_rma	1551.310s	167435.686us	3	3	100.00
	flash_ctrl_hw_rma_reset	952.520s	320270.686us	20	20	100.00
	flash_ctrl_lcmgr_intg	13.500s	24.413us	20	20	100.00
host_controller_arb				5	5	100.00
	flash_ctrl_host_ctrl_arb	1941.590s	260632.054us	5	5	100.00
erase_suspend				5	5	100.00
	flash_ctrl_erase_suspend	366.760s	6834.123us	5	5	100.00
program_reset				30	30	100.00
	flash_ctrl_prog_reset	208.570s	5758.064us	30	30	100.00
full_memory_access				5	5	100.00
	flash_ctrl_full_mem_access	3261.270s	50872.998us	5	5	100.00
rd_buff_eviction				5	5	100.00
	flash_ctrl_rd_buff_evict	110.310s	2763.934us	5	5	100.00
rd_buff_eviction_w_ecc				99	100	99.00
	flash_ctrl_rw_evict	31.540s	29.660us	40	40	100.00
	flash_ctrl_rw_evict_all_en	31.650s	65.745us	39	40	97.50
	flash_ctrl_re_evict	34.940s	135.102us	20	20	100.00
host_arb				19	20	95.00
	flash_ctrl_phy_arb	224.490s	737.922us	19	20	95.00
host_interleave				19	20	95.00
	flash_ctrl_phy_arb	224.490s	737.922us	19	20	95.00
memory_protection				20	20	100.00
	flash_ctrl_mp_regions	1030.180s	98041.303us	20	20	100.00
fetch_code				10	10	100.00
	flash_ctrl_fetch_code	25.450s	254.032us	10	10	100.00
all_partitions				20	20	100.00
	flash_ctrl_rand_ops	627.870s	824.217us	20	20	100.00
error_mp				10	10	100.00
	flash_ctrl_error_mp	644.870s	16939.785us	10	10	100.00
error_prog_win				10	10	100.00
	flash_ctrl_error_prog_win	552.380s	1380.769us	10	10	100.00
error_prog_type				5	5	100.00
	flash_ctrl_error_prog_type	1284.440s	750.790us	5	5	100.00
error_read_seed				20	20	100.00
	flash_ctrl_hw_read_seed_err	13.200s	77.507us	20	20	100.00
read_write_overflow				5	5	100.00
	flash_ctrl_oversize_error	162.120s	24475.352us	5	5	100.00
flash_ctrl_disable				50	50	100.00
	flash_ctrl_disable	21.960s	37.528us	50	50	100.00
flash_ctrl_connect				80	80	100.00
	flash_ctrl_connect	16.850s	77.428us	80	80	100.00
stress_all				5	5	100.00
	flash_ctrl_stress_all	1057.000s	2860.235us	5	5	100.00
secret_partition				129	130	99.23
	flash_ctrl_hw_sec_otp	179.220s	71793.008us	50	50	100.00
	flash_ctrl_otp_reset	117.360s	114.317us	79	80	98.75
isolation_partition				3	3	100.00
	flash_ctrl_hw_rma	1551.310s	167435.686us	3	3	100.00
interrupts				97	100	97.00
	flash_ctrl_intr_rd	242.010s	10640.043us	37	40	92.50
	flash_ctrl_intr_wr	84.940s	16607.856us	10	10	100.00
	flash_ctrl_intr_rd_slow_flash	388.150s	14492.391us	40	40	100.00
	flash_ctrl_intr_wr_slow_flash	476.740s	179474.101us	10	10	100.00
invalid_op				20	20	100.00
	flash_ctrl_invalid_op	84.300s	11860.576us	20	20	100.00
mid_op_rst				5	5	100.00
	flash_ctrl_mid_op_rst	81.120s	10612.172us	5	5	100.00
double_bit_err				35	35	100.00
	flash_ctrl_read_word_sweep_derr	17.340s	26.140us	5	5	100.00
	flash_ctrl_ro_derr	131.780s	728.939us	10	10	100.00
	flash_ctrl_rw_derr	196.870s	6152.859us	10	10	100.00
	flash_ctrl_derr_detect	150.260s	789.721us	5	5	100.00
	flash_ctrl_integrity	488.440s	8569.517us	5	5	100.00
single_bit_err				25	25	100.00
	flash_ctrl_read_word_sweep_serr	19.900s	37.513us	5	5	100.00
	flash_ctrl_ro_serr	124.850s	1538.896us	10	10	100.00
	flash_ctrl_rw_serr	205.940s	4815.113us	10	10	100.00
singlebit_err_counter				5	5	100.00
	flash_ctrl_serr_counter	76.730s	3952.596us	5	5	100.00
singlebit_err_address				5	5	100.00
	flash_ctrl_serr_address	85.210s	947.439us	5	5	100.00
scramble				60	62	96.77
	flash_ctrl_wo	218.910s	5742.537us	20	20	100.00
	flash_ctrl_write_word_sweep	10.550s	396.519us	1	1	100.00
	flash_ctrl_read_word_sweep	11.400s	104.904us	1	1	100.00
	flash_ctrl_ro	106.400s	1163.336us	19	20	95.00
	flash_ctrl_rw	488.670s	4912.012us	19	20	95.00
filesystem_support				5	5	100.00
	flash_ctrl_fs_sup	31.540s	350.327us	5	5	100.00
rma_write_process_error				23	23	100.00
	flash_ctrl_rma_err	947.950s	98867.353us	3	3	100.00
	flash_ctrl_hw_prog_rma_wipe_err	231.610s	10019.147us	20	20	100.00
alert_test				50	50	100.00
	flash_ctrl_alert_test	13.780s	683.302us	50	50	100.00
intr_test				50	50	100.00
	flash_ctrl_intr_test	13.240s	55.864us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	flash_ctrl_tl_errors	17.450s	63.365us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	flash_ctrl_tl_errors	17.450s	63.365us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	flash_ctrl_csr_hw_reset	19.880s	153.507us	5	5	100.00
	flash_ctrl_csr_rw	13.830s	29.856us	20	20	100.00
	flash_ctrl_csr_aliasing	54.840s	8830.915us	5	5	100.00
	flash_ctrl_same_csr_outstanding	21.430s	64.472us	20	20	100.00
tl_d_partial_access				50	50	100.00
	flash_ctrl_csr_hw_reset	19.880s	153.507us	5	5	100.00
	flash_ctrl_csr_rw	13.830s	29.856us	20	20	100.00
	flash_ctrl_csr_aliasing	54.840s	8830.915us	5	5	100.00
	flash_ctrl_same_csr_outstanding	21.430s	64.472us	20	20	100.00

V2S

481/485 passed

99.18 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
shadow_reg_update_error				20	20	100.00
	flash_ctrl_shadow_reg_errors	52.200s	73.573us	20	20	100.00
shadow_reg_read_clear_staged_value				20	20	100.00
	flash_ctrl_shadow_reg_errors	52.200s	73.573us	20	20	100.00
shadow_reg_storage_error				20	20	100.00
	flash_ctrl_shadow_reg_errors	52.200s	73.573us	20	20	100.00
shadowed_reset_glitch				20	20	100.00
	flash_ctrl_shadow_reg_errors	52.200s	73.573us	20	20	100.00
shadow_reg_update_error_with_csr_rw				20	20	100.00
	flash_ctrl_shadow_reg_errors_with_csr_rw	84.290s	749.017us	20	20	100.00
tl_intg_err				25	25	100.00
	flash_ctrl_tl_intg_err	552.520s	667.279us	20	20	100.00
	flash_ctrl_sec_cm	2338.990s	1135.090us	5	5	100.00
sec_cm_reg_bus_integrity				20	20	100.00
	flash_ctrl_tl_intg_err	552.520s	667.279us	20	20	100.00
sec_cm_host_bus_integrity				20	20	100.00
	flash_ctrl_tl_intg_err	552.520s	667.279us	20	20	100.00
sec_cm_mem_bus_integrity				6	6	100.00
	flash_ctrl_rd_intg	27.530s	111.956us	3	3	100.00
	flash_ctrl_wr_intg	12.590s	158.814us	3	3	100.00
sec_cm_scramble_key_sideload				50	50	100.00
	flash_ctrl_smoke	156.240s	1456.498us	50	50	100.00
sec_cm_lc_ctrl_intersig_mubi				259	260	99.62
	flash_ctrl_otp_reset	117.360s	114.317us	79	80	98.75
	flash_ctrl_disable	21.960s	37.528us	50	50	100.00
	flash_ctrl_sec_info_access	74.320s	8626.370us	50	50	100.00
	flash_ctrl_connect	16.850s	77.428us	80	80	100.00
sec_cm_ctrl_config_regwen				5	5	100.00
	flash_ctrl_config_regwen	12.130s	79.995us	5	5	100.00
sec_cm_data_regions_config_regwen				20	20	100.00
	flash_ctrl_csr_rw	13.830s	29.856us	20	20	100.00
sec_cm_data_regions_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	52.200s	73.573us	20	20	100.00
sec_cm_info_regions_config_regwen				20	20	100.00
	flash_ctrl_csr_rw	13.830s	29.856us	20	20	100.00
sec_cm_info_regions_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	52.200s	73.573us	20	20	100.00
sec_cm_bank_config_regwen				20	20	100.00
	flash_ctrl_csr_rw	13.830s	29.856us	20	20	100.00
sec_cm_bank_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	52.200s	73.573us	20	20	100.00
sec_cm_mem_ctrl_global_esc				50	50	100.00
	flash_ctrl_disable	21.960s	37.528us	50	50	100.00
sec_cm_mem_ctrl_local_esc				6	6	100.00
	flash_ctrl_rd_intg	27.530s	111.956us	3	3	100.00
	flash_ctrl_access_after_disable	12.940s	164.117us	3	3	100.00
sec_cm_mem_addr_infection				3	3	100.00
	flash_ctrl_host_addr_infection	25.240s	39.388us	3	3	100.00
sec_cm_mem_disable_config_mubi				50	50	100.00
	flash_ctrl_disable	21.960s	37.528us	50	50	100.00
sec_cm_exec_config_redun				10	10	100.00
	flash_ctrl_fetch_code	25.450s	254.032us	10	10	100.00
sec_cm_mem_scramble				19	20	95.00
	flash_ctrl_rw	488.670s	4912.012us	19	20	95.00
sec_cm_mem_integrity				25	25	100.00
	flash_ctrl_rw_serr	205.940s	4815.113us	10	10	100.00
	flash_ctrl_rw_derr	196.870s	6152.859us	10	10	100.00
	flash_ctrl_integrity	488.440s	8569.517us	5	5	100.00
sec_cm_rma_entry_mem_sec_wipe				3	3	100.00
	flash_ctrl_hw_rma	1551.310s	167435.686us	3	3	100.00
sec_cm_ctrl_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2338.990s	1135.090us	5	5	100.00
sec_cm_phy_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2338.990s	1135.090us	5	5	100.00
sec_cm_phy_prog_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2338.990s	1135.090us	5	5	100.00
sec_cm_ctr_redun				5	5	100.00
	flash_ctrl_sec_cm	2338.990s	1135.090us	5	5	100.00
sec_cm_phy_arbiter_ctrl_redun				5	5	100.00
	flash_ctrl_phy_arb_redun	18.790s	821.237us	5	5	100.00
sec_cm_phy_host_grant_ctrl_consistency				4	5	80.00
	flash_ctrl_phy_host_grant_err	11.950s	9.895us	4	5	80.00
sec_cm_phy_ack_ctrl_consistency				4	5	80.00
	flash_ctrl_phy_ack_consistency	13.240s	39.288us	4	5	80.00
sec_cm_fifo_ctr_redun				5	5	100.00
	flash_ctrl_sec_cm	2338.990s	1135.090us	5	5	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2338.990s	1135.090us	5	5	100.00
sec_cm_prog_tl_lc_gate_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2338.990s	1135.090us	5	5	100.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
asymmetric_read_path				1	1	100.00
	flash_ctrl_rd_ooo	23.440s	185.653us	1	1	100.00

unmapped

3/3 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				3	3	100.00
	flash_ctrl_basic_rw	348.860s	1488.100us	3	3	100.00

Error Messages

	Test	seed	line	log context
Job timed out after * minutes
	flash_ctrl_rw	66566955518984929994264119632092285041802021234884851093844114379232701148933	None	Job timed out after 60 minutes
Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))'
	flash_ctrl_phy_host_grant_err	112392719382822056220939577198388731013634854971224925129068840623923435208928	125	Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))' UVM_ERROR @ 9895.2 ns: (alert_esc_if.sv:201) [ASSERT FAILED] AlertKnown_A UVM_INFO @ 9895.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act () != exp ()
	flash_ctrl_phy_ack_consistency	31943280583176171485817259077750259276755339216085465139591665172924568573853	109	UVM_ERROR @ 20424.5 ns: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x2a) != exp (0x52) UVM_INFO @ 20424.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] : obs:exp ecf2a46_0eb99293:ffffffff_ffffffff mismatch!!
	flash_ctrl_intr_rd	41559267585209490072643457327954628855457290877142825900731065452587246676354	108	UVM_ERROR @ 7207532.6 ns: (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] 6: obs:exp 0ecf2a46_0eb99293:ffffffff_ffffffff mismatch!! UVM_INFO @ 7207532.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] : obs:exp d1ca_db2cabf5:ffffffff_db2cabf* mismatch!!
	flash_ctrl_intr_rd	15368161268712679682640278172514661727795547887531305577782505888782895601951	108	UVM_ERROR @ 12790242.8 ns: (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] 1: obs:exp 8933d1ca_db2cabf5:ffffffff_db2cabf5 mismatch!! UVM_INFO @ 12790242.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:267) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [] vs [*]) alert fatal_err triggered unexpectedly
	flash_ctrl_ro	92872930257059082062124567850601241486166096173225868584717592715055325837137	108	UVM_ERROR @ 3667598.5 ns: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly UVM_INFO @ 3667598.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_env_cfg.sv:714) [cfg] Check failed data[i] === exp_data[i] (* [] vs [*])
	flash_ctrl_phy_arb	92151221228477309095421448044475127564816635833549778545266566035296677296008	120	UVM_ERROR @ 35642.9 ns: (flash_ctrl_env_cfg.sv:714) [cfg] Check failed data[i] === exp_data[i] (0x37487266 [110111010010000111001001100110] vs 0xcb88cd8e [11001011100010001100110110001110]) UVM_INFO @ 35642.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: flash_ctrl_core_reg_block.op_status.err reset value:
	flash_ctrl_rw_evict_all_en	7945563256838061632920010214860101655100361188646840355621895293181061348426	108	UVM_ERROR @ 39110.6 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0 UVM_INFO @ 39110.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] : obs:exp e30273e3_5d9f3c73:ffffffff_5d9f3c mismatch!!
	flash_ctrl_intr_rd	21534129557092589492320788310976449373778683796121984310645386672867828067803	108	UVM_ERROR @ 3824843.4 ns: (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] 7: obs:exp e30273e3_5d9f3c73:ffffffff_5d9f3c73 mismatch!! UVM_INFO @ 3824843.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending 'dst_req_o'
	flash_ctrl_otp_reset	91324236292944580448351640033426394464641112815406073311168795765639186434370	185	Offending 'dst_req_o' UVM_ERROR @ 22888.1 ns: (prim_sync_reqack.sv:354) [ASSERT FAILED] SyncReqAckAckNeedsReq UVM_INFO @ 22888.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---