Simulation Results: hmac

 
02/05/2026 09:12:14 DVSim: v1.17.3 sha: 63c8a50 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 99.03 %
  • code
  • 99.29 %
  • assert
  • 97.80 %
  • func
  • 100.00 %
  • line
  • 99.90 %
  • branch
  • 99.83 %
  • cond
  • 96.74 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 14.270s 5185.613us 10 10 100.00
csr_hw_reset 5 5 100.00
hmac_csr_hw_reset 1.380s 193.383us 5 5 100.00
csr_rw 20 20 100.00
hmac_csr_rw 1.350s 30.554us 20 20 100.00
csr_bit_bash 5 5 100.00
hmac_csr_bit_bash 10.800s 323.212us 5 5 100.00
csr_aliasing 5 5 100.00
hmac_csr_aliasing 6.640s 675.331us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
hmac_csr_mem_rw_with_rand_reset 899.730s 312915.198us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
hmac_csr_rw 1.350s 30.554us 20 20 100.00
hmac_csr_aliasing 6.640s 675.331us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 103.490s 3167.687us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 98.510s 3916.756us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 277.120s 31751.363us 30 30 100.00
hmac_test_sha384_vectors 546.790s 30038.874us 75 75 100.00
hmac_test_sha512_vectors 543.310s 69910.789us 75 75 100.00
hmac_test_hmac256_vectors 16.450s 341.778us 50 50 100.00
hmac_test_hmac384_vectors 17.960s 452.517us 60 60 100.00
hmac_test_hmac512_vectors 20.840s 816.870us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 35.700s 8361.975us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 1318.770s 6481.084us 10 10 100.00
error 10 10 100.00
hmac_error 122.890s 6965.809us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 140.350s 2821.523us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 14.270s 5185.613us 10 10 100.00
hmac_long_msg 103.490s 3167.687us 10 10 100.00
hmac_back_pressure 98.510s 3916.756us 25 25 100.00
hmac_datapath_stress 1318.770s 6481.084us 10 10 100.00
hmac_burst_wr 35.700s 8361.975us 50 50 100.00
hmac_stress_all 2601.660s 306830.876us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 14.270s 5185.613us 10 10 100.00
hmac_long_msg 103.490s 3167.687us 10 10 100.00
hmac_back_pressure 98.510s 3916.756us 25 25 100.00
hmac_datapath_stress 1318.770s 6481.084us 10 10 100.00
hmac_wipe_secret 140.350s 2821.523us 10 10 100.00
hmac_test_sha256_vectors 277.120s 31751.363us 30 30 100.00
hmac_test_sha384_vectors 546.790s 30038.874us 75 75 100.00
hmac_test_sha512_vectors 543.310s 69910.789us 75 75 100.00
hmac_test_hmac256_vectors 16.450s 341.778us 50 50 100.00
hmac_test_hmac384_vectors 17.960s 452.517us 60 60 100.00
hmac_test_hmac512_vectors 20.840s 816.870us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 14.270s 5185.613us 10 10 100.00
hmac_long_msg 103.490s 3167.687us 10 10 100.00
hmac_back_pressure 98.510s 3916.756us 25 25 100.00
hmac_datapath_stress 1318.770s 6481.084us 10 10 100.00
hmac_burst_wr 35.700s 8361.975us 50 50 100.00
hmac_error 122.890s 6965.809us 10 10 100.00
hmac_wipe_secret 140.350s 2821.523us 10 10 100.00
hmac_test_sha256_vectors 277.120s 31751.363us 30 30 100.00
hmac_test_sha384_vectors 546.790s 30038.874us 75 75 100.00
hmac_test_sha512_vectors 543.310s 69910.789us 75 75 100.00
hmac_test_hmac256_vectors 16.450s 341.778us 50 50 100.00
hmac_test_hmac384_vectors 17.960s 452.517us 60 60 100.00
hmac_test_hmac512_vectors 20.840s 816.870us 75 75 100.00
hmac_stress_all 2601.660s 306830.876us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 2601.660s 306830.876us 50 50 100.00
alert_test 50 50 100.00
hmac_alert_test 0.940s 17.591us 50 50 100.00
intr_test 50 50 100.00
hmac_intr_test 0.980s 12.584us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
hmac_tl_errors 4.180s 201.900us 20 20 100.00
tl_d_illegal_access 20 20 100.00
hmac_tl_errors 4.180s 201.900us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
hmac_csr_hw_reset 1.380s 193.383us 5 5 100.00
hmac_csr_rw 1.350s 30.554us 20 20 100.00
hmac_csr_aliasing 6.640s 675.331us 5 5 100.00
hmac_same_csr_outstanding 2.550s 107.355us 20 20 100.00
tl_d_partial_access 50 50 100.00
hmac_csr_hw_reset 1.380s 193.383us 5 5 100.00
hmac_csr_rw 1.350s 30.554us 20 20 100.00
hmac_csr_aliasing 6.640s 675.331us 5 5 100.00
hmac_same_csr_outstanding 2.550s 107.355us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
hmac_tl_intg_err 5.370s 1118.483us 20 20 100.00
hmac_sec_cm 1.440s 191.146us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
hmac_tl_intg_err 5.370s 1118.483us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 14.270s 5185.613us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 8.590s 550.260us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 985.230s 65412.022us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.030s 15.846us 1 1 100.00