Simulation Results: kmac/masked

 
02/05/2026 09:12:14 DVSim: v1.17.3 sha: 63c8a50 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.74 %
  • code
  • 94.25 %
  • assert
  • 97.98 %
  • func
  • 97.99 %
  • line
  • 99.25 %
  • branch
  • 97.08 %
  • cond
  • 94.76 %
  • toggle
  • 99.89 %
  • FSM
  • 80.28 %
Validation stages
V1
100.00%
V2
99.87%
V2S
100.00%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
kmac_smoke 79.660s 4129.487us 50 50 100.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 1.510s 125.124us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.580s 29.268us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 13.450s 1022.479us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 6.000s 139.352us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 2.650s 76.507us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.580s 29.268us 20 20 100.00
kmac_csr_aliasing 6.000s 139.352us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 1.030s 14.053us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 2.070s 139.110us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 3388.860s 583203.524us 50 50 100.00
burst_write 50 50 100.00
kmac_burst_write 1254.210s 14927.323us 50 50 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 2103.070s 64250.198us 5 5 100.00
kmac_test_vectors_sha3_256 2184.530s 358655.576us 5 5 100.00
kmac_test_vectors_sha3_384 1458.880s 154564.791us 5 5 100.00
kmac_test_vectors_sha3_512 1336.070s 46906.522us 5 5 100.00
kmac_test_vectors_shake_128 2022.240s 21309.492us 5 5 100.00
kmac_test_vectors_shake_256 1774.460s 700190.753us 5 5 100.00
kmac_test_vectors_kmac 3.830s 274.097us 5 5 100.00
kmac_test_vectors_kmac_xof 3.740s 369.256us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 432.130s 22037.590us 50 50 100.00
app 50 50 100.00
kmac_app 347.510s 54507.891us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 305.990s 75516.208us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 367.210s 18906.214us 50 50 100.00
error 50 50 100.00
kmac_error 431.720s 69236.928us 50 50 100.00
key_error 50 50 100.00
kmac_key_error 19.110s 7103.907us 50 50 100.00
sideload_invalid 50 50 100.00
kmac_sideload_invalid 9.840s 1143.342us 50 50 100.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 41.420s 5844.886us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 36.250s 1803.274us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 55.690s 20642.960us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 43.530s 2949.923us 50 50 100.00
stress_all 49 50 98.00
kmac_stress_all 2853.810s 111112.054us 49 50 98.00
intr_test 50 50 100.00
kmac_intr_test 1.250s 52.701us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.390s 183.228us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 4.040s 150.413us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 4.040s 150.413us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 1.510s 125.124us 5 5 100.00
kmac_csr_rw 1.580s 29.268us 20 20 100.00
kmac_csr_aliasing 6.000s 139.352us 5 5 100.00
kmac_same_csr_outstanding 3.310s 115.525us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 1.510s 125.124us 5 5 100.00
kmac_csr_rw 1.580s 29.268us 20 20 100.00
kmac_csr_aliasing 6.000s 139.352us 5 5 100.00
kmac_same_csr_outstanding 3.310s 115.525us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.600s 119.537us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.600s 119.537us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.600s 119.537us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.600s 119.537us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
kmac_shadow_reg_errors_with_csr_rw 4.840s 929.277us 20 20 100.00
tl_intg_err 25 25 100.00
kmac_tl_intg_err 5.760s 261.252us 20 20 100.00
kmac_sec_cm 110.760s 28754.634us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 5.760s 261.252us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 43.530s 2949.923us 50 50 100.00
sec_cm_sw_key_key_masking 50 50 100.00
kmac_smoke 79.660s 4129.487us 50 50 100.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 432.130s 22037.590us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.600s 119.537us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 110.760s 28754.634us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 110.760s 28754.634us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 110.760s 28754.634us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 50 50 100.00
kmac_smoke 79.660s 4129.487us 50 50 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 43.530s 2949.923us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 110.760s 28754.634us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 341.150s 27583.917us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 50 50 100.00
kmac_smoke 79.660s 4129.487us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 9 10 90.00
kmac_stress_all_with_rand_reset 195.590s 7053.807us 9 10 90.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:847) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*])
kmac_stress_all_with_rand_reset 82010336659973808587789898093864766165754515619722036387935744328694854941601 229
UVM_ERROR @ 8560621631 ps: (cip_base_vseq.sv:847) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 8560621631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: *
kmac_stress_all 26645073676363213259738345208713486408265888463161781515303380427734056530843 252
UVM_ERROR @ 33208819936 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 33208819936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---