Simulation Results: kmac/unmasked

 
02/05/2026 09:12:14 DVSim: v1.17.3 sha: 63c8a50 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.56 %
  • code
  • 92.54 %
  • assert
  • 97.90 %
  • func
  • 96.25 %
  • line
  • 97.65 %
  • branch
  • 95.93 %
  • cond
  • 94.75 %
  • toggle
  • 100.00 %
  • FSM
  • 74.38 %
Validation stages
V1
100.00%
V2
98.70%
V2S
100.00%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
kmac_smoke 69.310s 30039.034us 50 50 100.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 1.540s 276.401us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.590s 96.245us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 17.870s 2994.128us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 8.290s 5402.811us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 3.200s 72.160us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.590s 96.245us 20 20 100.00
kmac_csr_aliasing 8.290s 5402.811us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 1.040s 33.607us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.920s 130.163us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 2657.090s 440754.020us 50 50 100.00
burst_write 50 50 100.00
kmac_burst_write 938.360s 131868.270us 50 50 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 2005.100s 97097.146us 5 5 100.00
kmac_test_vectors_sha3_256 2003.090s 115241.603us 5 5 100.00
kmac_test_vectors_sha3_384 1574.080s 197145.816us 5 5 100.00
kmac_test_vectors_sha3_512 1103.560s 46878.824us 5 5 100.00
kmac_test_vectors_shake_128 2072.940s 279215.869us 5 5 100.00
kmac_test_vectors_shake_256 1980.150s 58440.031us 5 5 100.00
kmac_test_vectors_kmac 2.730s 121.447us 5 5 100.00
kmac_test_vectors_kmac_xof 2.910s 111.287us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 426.820s 91863.072us 50 50 100.00
app 50 50 100.00
kmac_app 334.930s 65154.990us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 232.890s 30321.177us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 338.280s 17165.850us 50 50 100.00
error 50 50 100.00
kmac_error 464.650s 21258.722us 50 50 100.00
key_error 50 50 100.00
kmac_key_error 18.430s 12252.509us 50 50 100.00
sideload_invalid 40 50 80.00
kmac_sideload_invalid 123.400s 10025.540us 40 50 80.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 38.820s 2092.869us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 43.090s 1680.742us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 47.310s 16904.256us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 19.180s 945.654us 50 50 100.00
stress_all 50 50 100.00
kmac_stress_all 2451.520s 116178.627us 50 50 100.00
intr_test 50 50 100.00
kmac_intr_test 1.160s 16.931us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.240s 74.492us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 4.350s 142.364us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 4.350s 142.364us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 1.540s 276.401us 5 5 100.00
kmac_csr_rw 1.590s 96.245us 20 20 100.00
kmac_csr_aliasing 8.290s 5402.811us 5 5 100.00
kmac_same_csr_outstanding 3.050s 99.193us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 1.540s 276.401us 5 5 100.00
kmac_csr_rw 1.590s 96.245us 20 20 100.00
kmac_csr_aliasing 8.290s 5402.811us 5 5 100.00
kmac_same_csr_outstanding 3.050s 99.193us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.360s 100.755us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.360s 100.755us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.360s 100.755us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.360s 100.755us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
kmac_shadow_reg_errors_with_csr_rw 6.280s 225.020us 20 20 100.00
tl_intg_err 25 25 100.00
kmac_tl_intg_err 5.520s 444.040us 20 20 100.00
kmac_sec_cm 85.260s 17785.895us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 5.520s 444.040us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 19.180s 945.654us 50 50 100.00
sec_cm_sw_key_key_masking 50 50 100.00
kmac_smoke 69.310s 30039.034us 50 50 100.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 426.820s 91863.072us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.360s 100.755us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 85.260s 17785.895us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 85.260s 17785.895us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 85.260s 17785.895us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 50 50 100.00
kmac_smoke 69.310s 30039.034us 50 50 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 19.180s 945.654us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 85.260s 17785.895us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 261.090s 12748.209us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 50 50 100.00
kmac_smoke 69.310s 30039.034us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 9 10 90.00
kmac_stress_all_with_rand_reset 177.970s 13170.486us 9 10 90.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15)
kmac_sideload_invalid 43489755877340345269753388328323784062489621260029726285066602186900630327770 93
UVM_FATAL @ 10363044243 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xf0c69000, Comparison=CompareOpEq, exp_data=0x1, call_count=15)
UVM_INFO @ 10363044243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4)
kmac_sideload_invalid 35171674933235530197614048408822522517714917006156008391958980405302263285009 81
UVM_FATAL @ 10025539888 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x5a8e0000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
UVM_INFO @ 10025539888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
kmac_stress_all_with_rand_reset 67930825097192521808574788351527621729331539291629797160040135888661324007072 277
UVM_ERROR @ 8164498867 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 8164498867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9)
kmac_sideload_invalid 96456535130223680129658639093438730827008331100431169282282254304649673795961 88
UVM_FATAL @ 10101864816 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x94c34000, Comparison=CompareOpEq, exp_data=0x1, call_count=9)
UVM_INFO @ 10101864816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 29530593534525152741695035392467818734789928779074750135258693989248880248161 86
UVM_FATAL @ 10062486313 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xc28ef000, Comparison=CompareOpEq, exp_data=0x1, call_count=9)
UVM_INFO @ 10062486313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=24)
kmac_sideload_invalid 78773911587653828720585767222178035565351388581156373158832736310710307248693 100
UVM_FATAL @ 10152417822 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x7d9f5000, Comparison=CompareOpEq, exp_data=0x1, call_count=24)
UVM_INFO @ 10152417822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2)
kmac_sideload_invalid 55178903850637207113050935030902580020803430069892379751924272313806792869975 78
UVM_FATAL @ 10010065826 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x8a1b4000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10010065826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 102655405845586730640863048154481679973871866904316075683285955695859667681055 78
UVM_FATAL @ 10019992646 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xbd134000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10019992646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3)
kmac_sideload_invalid 68357273437773526012558303140565691614129013950157079045235443477122795617525 79
UVM_FATAL @ 10044497736 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xa15a5000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 10044497736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7)
kmac_sideload_invalid 46003103304943888606986920990468166152346063689301977545636541013377007106441 84
UVM_FATAL @ 10243282368 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x2329a000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
UVM_INFO @ 10243282368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 105663031151607509330239483058924003576769909541724468650869228177653075534279 89
UVM_FATAL @ 10060913424 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x637b8000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
UVM_INFO @ 10060913424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---