Simulation Results: lc_ctrl/volatile_unlock_disabled

 
02/05/2026 09:12:14 DVSim: v1.17.3 sha: 63c8a50 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.30 %
  • code
  • 86.37 %
  • assert
  • 94.27 %
  • func
  • 96.26 %
  • line
  • 97.26 %
  • branch
  • 94.27 %
  • cond
  • 81.64 %
  • toggle
  • 89.54 %
  • FSM
  • 69.16 %
Validation stages
V1
100.00%
V2
99.04%
V2S
100.00%
V3
44.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
lc_ctrl_smoke 9.950s 887.669us 50 50 100.00
csr_hw_reset 5 5 100.00
lc_ctrl_csr_hw_reset 1.550s 116.174us 5 5 100.00
csr_rw 20 20 100.00
lc_ctrl_csr_rw 1.230s 45.672us 20 20 100.00
csr_bit_bash 5 5 100.00
lc_ctrl_csr_bit_bash 1.870s 54.157us 5 5 100.00
csr_aliasing 5 5 100.00
lc_ctrl_csr_aliasing 1.630s 184.922us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.070s 65.946us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
lc_ctrl_csr_rw 1.230s 45.672us 20 20 100.00
lc_ctrl_csr_aliasing 1.630s 184.922us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 50 50 100.00
lc_ctrl_state_post_trans 8.830s 350.762us 50 50 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 16.130s 345.594us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.330s 13.331us 10 10 100.00
lc_prog_failure 50 50 100.00
lc_ctrl_prog_failure 4.500s 442.587us 50 50 100.00
lc_state_failure 50 50 100.00
lc_ctrl_state_failure 14.500s 225.804us 50 50 100.00
lc_errors 45 50 90.00
lc_ctrl_errors 14.960s 569.418us 45 50 90.00
security_escalation 254 260 97.69
lc_ctrl_state_failure 14.500s 225.804us 50 50 100.00
lc_ctrl_prog_failure 4.500s 442.587us 50 50 100.00
lc_ctrl_errors 14.960s 569.418us 45 50 90.00
lc_ctrl_security_escalation 12.390s 531.218us 50 50 100.00
lc_ctrl_jtag_state_failure 68.760s 2841.495us 20 20 100.00
lc_ctrl_jtag_prog_failure 11.040s 1969.870us 20 20 100.00
lc_ctrl_jtag_errors 82.650s 8232.818us 19 20 95.00
jtag_access 209 210 99.52
lc_ctrl_jtag_smoke 13.530s 965.595us 20 20 100.00
lc_ctrl_jtag_state_post_trans 22.900s 766.647us 20 20 100.00
lc_ctrl_jtag_prog_failure 11.040s 1969.870us 20 20 100.00
lc_ctrl_jtag_errors 82.650s 8232.818us 19 20 95.00
lc_ctrl_jtag_access 15.520s 663.639us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 24.900s 1417.245us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 3.870s 212.517us 10 10 100.00
lc_ctrl_jtag_csr_rw 2.890s 477.526us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 40.460s 2643.859us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 9.540s 2950.690us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.430s 141.098us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 5.210s 294.282us 10 10 100.00
lc_ctrl_jtag_alert_test 2.620s 89.690us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 18.210s 7852.623us 10 10 100.00
lc_ctrl_volatile_unlock 50 50 100.00
lc_ctrl_volatile_unlock_smoke 1.690s 28.026us 50 50 100.00
stress_all 49 50 98.00
lc_ctrl_stress_all 495.950s 55450.581us 49 50 98.00
alert_test 50 50 100.00
lc_ctrl_alert_test 1.870s 173.899us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
lc_ctrl_tl_errors 3.700s 2144.222us 20 20 100.00
tl_d_illegal_access 20 20 100.00
lc_ctrl_tl_errors 3.700s 2144.222us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.550s 116.174us 5 5 100.00
lc_ctrl_csr_rw 1.230s 45.672us 20 20 100.00
lc_ctrl_csr_aliasing 1.630s 184.922us 5 5 100.00
lc_ctrl_same_csr_outstanding 2.060s 127.432us 20 20 100.00
tl_d_partial_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.550s 116.174us 5 5 100.00
lc_ctrl_csr_rw 1.230s 45.672us 20 20 100.00
lc_ctrl_csr_aliasing 1.630s 184.922us 5 5 100.00
lc_ctrl_same_csr_outstanding 2.060s 127.432us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
lc_ctrl_sec_cm 12.130s 996.133us 5 5 100.00
lc_ctrl_tl_intg_err 2.570s 486.169us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
lc_ctrl_tl_intg_err 2.570s 486.169us 20 20 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 16.130s 345.594us 10 10 100.00
sec_cm_manuf_state_sparse 55 55 100.00
lc_ctrl_state_failure 14.500s 225.804us 50 50 100.00
lc_ctrl_sec_cm 12.130s 996.133us 5 5 100.00
sec_cm_transition_ctr_sparse 55 55 100.00
lc_ctrl_state_failure 14.500s 225.804us 50 50 100.00
lc_ctrl_sec_cm 12.130s 996.133us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 14.500s 225.804us 50 50 100.00
lc_ctrl_sec_cm 12.130s 996.133us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 14.500s 225.804us 50 50 100.00
lc_ctrl_sec_cm 12.130s 996.133us 5 5 100.00
sec_cm_state_config_sparse 55 55 100.00
lc_ctrl_state_failure 14.500s 225.804us 50 50 100.00
lc_ctrl_sec_cm 12.130s 996.133us 5 5 100.00
sec_cm_main_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 14.500s 225.804us 50 50 100.00
lc_ctrl_sec_cm 12.130s 996.133us 5 5 100.00
sec_cm_kmac_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 14.500s 225.804us 50 50 100.00
lc_ctrl_sec_cm 12.130s 996.133us 5 5 100.00
sec_cm_main_fsm_local_esc 55 55 100.00
lc_ctrl_state_failure 14.500s 225.804us 50 50 100.00
lc_ctrl_sec_cm 12.130s 996.133us 5 5 100.00
sec_cm_main_fsm_global_esc 50 50 100.00
lc_ctrl_security_escalation 12.390s 531.218us 50 50 100.00
sec_cm_main_ctrl_flow_consistency 70 70 100.00
lc_ctrl_state_post_trans 8.830s 350.762us 50 50 100.00
lc_ctrl_jtag_state_post_trans 22.900s 766.647us 20 20 100.00
sec_cm_intersig_mubi 50 50 100.00
lc_ctrl_sec_mubi 12.330s 778.576us 50 50 100.00
sec_cm_token_valid_ctrl_mubi 50 50 100.00
lc_ctrl_sec_mubi 12.330s 778.576us 50 50 100.00
sec_cm_token_digest 50 50 100.00
lc_ctrl_sec_token_digest 17.440s 4382.921us 50 50 100.00
sec_cm_token_mux_ctrl_redun 50 50 100.00
lc_ctrl_sec_token_mux 12.500s 735.557us 50 50 100.00
sec_cm_token_valid_mux_redun 50 50 100.00
lc_ctrl_sec_token_mux 12.500s 735.557us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 22 50 44.00
lc_ctrl_stress_all_with_rand_reset 126.350s 4549.862us 22 50 44.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 27081511098279747541589227286165227542280708666264051218923387643945222605756 6726
UVM_ERROR @ 4126361031 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4126361031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 76587128684316688423007985697684264886861489477216664071355840448857351626358 210
UVM_ERROR @ 484490184 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 484490184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 84836245901674073894689683983932430314350073736754175214551173531602024184402 6546
UVM_ERROR @ 9923765944 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 9923765944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 68552082558285412150362526604846252354579449020152956134028634726572636750884 446
UVM_ERROR @ 1589206962 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1589206962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 87311511861029675777450026404123137165771456576921950328828039280761353687445 162
UVM_ERROR @ 1862359264 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1862359264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 73839133323372031175790146700080011054920701001898265355666335520206560107246 150
UVM_ERROR @ 107854523 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 107854523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 51328697644795685397375640935906065515999495101472409591214635549337796522166 1705
UVM_ERROR @ 445886726 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 445886726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 49753620417547633064678990376935579125046049288284348211403623450277653540562 257
UVM_ERROR @ 1713604599 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1713604599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 90443297249189570224556540089473088825038158937829524047619093328522891355068 9164
UVM_ERROR @ 41955692824 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 41955692824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 35534258983148530948387618172678143106620439341655256125955497975387868104944 2551
UVM_ERROR @ 9294347703 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 9294347703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 47439675573070791072047791289267807961877259612740346063939092094314667795958 5714
UVM_ERROR @ 10548768418 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 10548768418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 1117400842890418407095477509209747480310560152333407022017639336234253911235 906
UVM_ERROR @ 6518332052 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 6518332052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 37713849518896789597090644907436407513042550942334768621994609811712178042182 198
UVM_ERROR @ 213624393 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 213624393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 8750573249356644903663700443737310002309628279963747916015158191719711432054 18681
UVM_ERROR @ 7688170777 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 7688170777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 69601425842850245057329502888556430858214606446749384225795206178153900555862 198
UVM_ERROR @ 108024906 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 108024906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 44619617546545693464133265588086288582398793117407587001851861405205930915181 4103
UVM_ERROR @ 969723421 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 969723421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 35178176718227463753102393870945123368384157719573026257107481411701700613379 1745
UVM_ERROR @ 1861728377 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1861728377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 115086652558394331262734516649132257410264596589715099310183000519375164539145 1370
UVM_ERROR @ 2238968933 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2238968933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 71284922155850174436934082878009333229040109822435979247306310925395972241141 8415
UVM_ERROR @ 9172525882 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 9172525882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 37631031636565152644862525000769683608470343631654862802931911934529927440963 904
UVM_ERROR @ 3013779180 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3013779180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 58834665889352890740611719165256351318747947177652199275040724094340454736236 151
UVM_ERROR @ 528837933 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 528837933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 18152287305148597032649085153619361675878232414129142054118430913462347397507 644
UVM_ERROR @ 6316568696 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 6316568696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 20456987719567642377021948528669896638121812183564141991931869594752392177199 7892
UVM_ERROR @ 3283057579 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3283057579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 38977745766110603865689278815717166234814260086282398789872544753899112385383 197
UVM_ERROR @ 110587070 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 110587070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 81647165343893851746015768891994618923360807050179444258801747472043396225990 15069
UVM_ERROR @ 4096487873 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4096487873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 25050645478620379937175553998135112722634725242924299945614144657785866639144 656
UVM_ERROR @ 6384517974 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10003 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 6384517974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 35303523265265098878782811901869814475874001332723613424244620731008839015212 2467
UVM_ERROR @ 7803154836 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 7803154836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*])
lc_ctrl_errors 115499085245327200636181060712496928083734689812168277476089968232787504703173 258
UVM_ERROR @ 24152645 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 24152645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_errors 78695019811237582864085591165163027613961103989248118154972207422045888200482 1208
UVM_ERROR @ 2267208079 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 2267208079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 98681770566176266041416815620208552289124240973826685785340663286610655396238 2385
UVM_ERROR @ 2624334837 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 2624334837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 44059044670428142168937088533070969601883234157263696036382255083507227814572 3002
UVM_ERROR @ 186404550 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 186404550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 78764073901325859310780801170328460819931587050493570143319829515257750074887 1767
UVM_ERROR @ 314830356 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 314830356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 102106352172794886386233890525524712313420900477625555040330891988958370824661 311
UVM_ERROR @ 75295009 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 75295009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 87563123051093812183575369529704150776558838546115538110225793675207974273144 3574
UVM_ERROR @ 7907832250 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 7907832250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_scoreboard.sv:248) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestLocked*
lc_ctrl_stress_all_with_rand_reset 61025194844269133358707478586984290630286619568400426333645984899935028192015 995
UVM_ERROR @ 2073870752 ps: (lc_ctrl_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (10 [0xa] vs 5 [0x5]) Called from line: 105, LC_St DecLcStTestLocked4
UVM_INFO @ 2073870752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---