Simulation Results: lc_ctrl/volatile_unlock_enabled

 
02/05/2026 09:12:14 DVSim: v1.17.3 sha: 63c8a50 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.37 %
  • code
  • 86.41 %
  • assert
  • 94.27 %
  • func
  • 96.44 %
  • line
  • 97.24 %
  • branch
  • 94.36 %
  • cond
  • 81.77 %
  • toggle
  • 89.54 %
  • FSM
  • 69.16 %
Validation stages
V1
100.00%
V2
99.18%
V2S
100.00%
V3
46.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
lc_ctrl_smoke 6.490s 251.614us 50 50 100.00
csr_hw_reset 5 5 100.00
lc_ctrl_csr_hw_reset 1.410s 15.555us 5 5 100.00
csr_rw 20 20 100.00
lc_ctrl_csr_rw 1.330s 15.208us 20 20 100.00
csr_bit_bash 5 5 100.00
lc_ctrl_csr_bit_bash 2.590s 353.700us 5 5 100.00
csr_aliasing 5 5 100.00
lc_ctrl_csr_aliasing 1.580s 95.737us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.830s 36.273us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
lc_ctrl_csr_rw 1.330s 15.208us 20 20 100.00
lc_ctrl_csr_aliasing 1.580s 95.737us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 50 50 100.00
lc_ctrl_state_post_trans 8.960s 203.855us 50 50 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 21.930s 829.743us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.210s 53.011us 10 10 100.00
lc_prog_failure 50 50 100.00
lc_ctrl_prog_failure 4.200s 426.515us 50 50 100.00
lc_state_failure 50 50 100.00
lc_ctrl_state_failure 14.790s 474.870us 50 50 100.00
lc_errors 49 50 98.00
lc_ctrl_errors 16.100s 5272.162us 49 50 98.00
security_escalation 257 260 98.85
lc_ctrl_state_failure 14.790s 474.870us 50 50 100.00
lc_ctrl_prog_failure 4.200s 426.515us 50 50 100.00
lc_ctrl_errors 16.100s 5272.162us 49 50 98.00
lc_ctrl_security_escalation 10.810s 355.106us 50 50 100.00
lc_ctrl_jtag_state_failure 82.630s 31637.286us 20 20 100.00
lc_ctrl_jtag_prog_failure 19.510s 3490.229us 20 20 100.00
lc_ctrl_jtag_errors 52.770s 10165.940us 18 20 90.00
jtag_access 208 210 99.05
lc_ctrl_jtag_smoke 13.580s 683.302us 20 20 100.00
lc_ctrl_jtag_state_post_trans 24.370s 1737.125us 20 20 100.00
lc_ctrl_jtag_prog_failure 19.510s 3490.229us 20 20 100.00
lc_ctrl_jtag_errors 52.770s 10165.940us 18 20 90.00
lc_ctrl_jtag_access 18.560s 972.982us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 30.650s 2621.504us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 3.700s 631.675us 10 10 100.00
lc_ctrl_jtag_csr_rw 2.350s 149.649us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 24.700s 6070.400us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 17.720s 979.789us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.630s 192.031us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.460s 383.209us 10 10 100.00
lc_ctrl_jtag_alert_test 1.520s 102.139us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 54.810s 12146.571us 10 10 100.00
lc_ctrl_volatile_unlock 49 50 98.00
lc_ctrl_volatile_unlock_smoke 1.610s 39.136us 49 50 98.00
stress_all 48 50 96.00
lc_ctrl_stress_all 496.170s 21775.026us 48 50 96.00
alert_test 50 50 100.00
lc_ctrl_alert_test 2.340s 71.288us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
lc_ctrl_tl_errors 4.250s 327.728us 20 20 100.00
tl_d_illegal_access 20 20 100.00
lc_ctrl_tl_errors 4.250s 327.728us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.410s 15.555us 5 5 100.00
lc_ctrl_csr_rw 1.330s 15.208us 20 20 100.00
lc_ctrl_csr_aliasing 1.580s 95.737us 5 5 100.00
lc_ctrl_same_csr_outstanding 1.800s 80.697us 20 20 100.00
tl_d_partial_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.410s 15.555us 5 5 100.00
lc_ctrl_csr_rw 1.330s 15.208us 20 20 100.00
lc_ctrl_csr_aliasing 1.580s 95.737us 5 5 100.00
lc_ctrl_same_csr_outstanding 1.800s 80.697us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
lc_ctrl_sec_cm 9.280s 887.277us 5 5 100.00
lc_ctrl_tl_intg_err 2.950s 456.383us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
lc_ctrl_tl_intg_err 2.950s 456.383us 20 20 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 21.930s 829.743us 10 10 100.00
sec_cm_manuf_state_sparse 55 55 100.00
lc_ctrl_state_failure 14.790s 474.870us 50 50 100.00
lc_ctrl_sec_cm 9.280s 887.277us 5 5 100.00
sec_cm_transition_ctr_sparse 55 55 100.00
lc_ctrl_state_failure 14.790s 474.870us 50 50 100.00
lc_ctrl_sec_cm 9.280s 887.277us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 14.790s 474.870us 50 50 100.00
lc_ctrl_sec_cm 9.280s 887.277us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 14.790s 474.870us 50 50 100.00
lc_ctrl_sec_cm 9.280s 887.277us 5 5 100.00
sec_cm_state_config_sparse 55 55 100.00
lc_ctrl_state_failure 14.790s 474.870us 50 50 100.00
lc_ctrl_sec_cm 9.280s 887.277us 5 5 100.00
sec_cm_main_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 14.790s 474.870us 50 50 100.00
lc_ctrl_sec_cm 9.280s 887.277us 5 5 100.00
sec_cm_kmac_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 14.790s 474.870us 50 50 100.00
lc_ctrl_sec_cm 9.280s 887.277us 5 5 100.00
sec_cm_main_fsm_local_esc 55 55 100.00
lc_ctrl_state_failure 14.790s 474.870us 50 50 100.00
lc_ctrl_sec_cm 9.280s 887.277us 5 5 100.00
sec_cm_main_fsm_global_esc 50 50 100.00
lc_ctrl_security_escalation 10.810s 355.106us 50 50 100.00
sec_cm_main_ctrl_flow_consistency 70 70 100.00
lc_ctrl_state_post_trans 8.960s 203.855us 50 50 100.00
lc_ctrl_jtag_state_post_trans 24.370s 1737.125us 20 20 100.00
sec_cm_intersig_mubi 50 50 100.00
lc_ctrl_sec_mubi 12.670s 1001.718us 50 50 100.00
sec_cm_token_valid_ctrl_mubi 50 50 100.00
lc_ctrl_sec_mubi 12.670s 1001.718us 50 50 100.00
sec_cm_token_digest 50 50 100.00
lc_ctrl_sec_token_digest 15.160s 4595.484us 50 50 100.00
sec_cm_token_mux_ctrl_redun 50 50 100.00
lc_ctrl_sec_token_mux 12.950s 790.360us 50 50 100.00
sec_cm_token_valid_mux_redun 50 50 100.00
lc_ctrl_sec_token_mux 12.950s 790.360us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 23 50 46.00
lc_ctrl_stress_all_with_rand_reset 130.190s 82355.824us 23 50 46.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 53598603425859670402524113458774477735857091597298544914408450535267897197060 157
UVM_ERROR @ 2762701595 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2762701595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 15859727823773767060557553752481439014137039962790457503329504802785268859378 5164
UVM_ERROR @ 3301368821 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3301368821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 28141428078540249015945052933766231252051891068874916144911540817101448257321 175
UVM_ERROR @ 866403707 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 866403707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 102561423075611985070460665243413521518533521555411478864851485170420342366073 180
UVM_ERROR @ 1305742537 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1305742537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 15353269767189019468656092945741623862541457826573014285601427359864041043631 4450
UVM_ERROR @ 9891772008 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 9891772008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 74187992046532405498308888725973816414229227013141367285262580015271529619451 155
UVM_ERROR @ 632614341 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 632614341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 79343586386282308139259650349972582754903980332860072198715394466507547410552 159
UVM_ERROR @ 3786668399 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3786668399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 96098752734097752570128845955405032274989894366188418505065996994181748289064 3191
UVM_ERROR @ 2139947432 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2139947432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 40067896918896952660257444826652369783849860108417937335675268576972371633651 1423
UVM_ERROR @ 6361636548 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 6361636548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 85815578210302461657794739822897688918968634105547046882073445081895305703748 195
UVM_ERROR @ 432138772 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 432138772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 11593880049541218075921482176283458850227250224861709722773897838385710031808 205
UVM_ERROR @ 548089686 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 548089686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 76367158768635899012241389184319364390656949498015216278596334488078002000043 433
UVM_ERROR @ 2063004367 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2063004367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 26166432140504427717948242825394551614710360921350672026722843907937738489819 2090
UVM_ERROR @ 5889731282 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5889731282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 31563695106708523633427344450826132468644167417783771959242306686554780015572 5504
UVM_ERROR @ 2451500841 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2451500841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 39420992189645803225098189779991099180152072094845706419302717873497793877360 518
UVM_ERROR @ 9734901310 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 9734901310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 16096447139776143789030948056953470127025801465600858490336962961274931256120 150
UVM_ERROR @ 699191773 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 699191773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 98321089072946117782755116077597368389216648645371584274719449411752577912368 234
UVM_ERROR @ 3561925464 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3561925464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 18895155411303452507659816147094871576073841114389970331153629451696812778671 1326
UVM_ERROR @ 660940867 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 660940867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 91901923852563333071813495069261085214155322380950163187041238613131091282551 7354
UVM_ERROR @ 3475107298 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3475107298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 82370469246325675670314820142833309549940562047960219093572191578538491813705 2746
UVM_ERROR @ 337795965 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 337795965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 15193213246729488050617908351919665665064360573164135716017005936666524010061 649
UVM_ERROR @ 5586629453 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5586629453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 42286824310153362395978703004567833833940237646752849760126858402888790199775 4483
UVM_ERROR @ 448079796 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 448079796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 33838122572409925666190414665975179591916262888684443903040142456650218226249 9557
UVM_ERROR @ 4932555500 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4932555500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 99962321013971795867007578298825286026403417184300700863107481700971973781827 3043
UVM_ERROR @ 2887603913 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2887603913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*])
lc_ctrl_stress_all 8622766716167919575753567688663845583321695773784323608848737159263823413245 5140
UVM_ERROR @ 1809683899 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1809683899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_errors 76749453387077663909655040304048561334652984654138033476227005485330647658147 194
UVM_ERROR @ 120290489 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 120290489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_errors 110588216327369446082223998345814945012118383659671026073497610748883975718330 2767
UVM_ERROR @ 2582626869 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 2582626869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 27005973363506254028239645985735497489360016447012111192154234718946194812516 9385
UVM_ERROR @ 21021499950 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 21021499950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 65165731792232381232242029506565238638540672880569202034337739444727912762407 3260
UVM_ERROR @ 1154086639 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1154086639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
lc_ctrl_stress_all_with_rand_reset 39907650824707505649253029170270817257646164131531344944445754816921181362844 9850
UVM_ERROR @ 2650257727 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
UVM_INFO @ 2650257727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 86477960436593360831539198177620002614417534639072099224778930693823227014143 14167
UVM_ERROR @ 32330178614 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
UVM_INFO @ 32330178614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 304782038223520512556439684300556943663495547055007944641170379102998970738 5666
UVM_ERROR @ 14604424320 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
UVM_INFO @ 14604424320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout lc_ctrl_regs_reg_block.status.transition_successful (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2)
lc_ctrl_volatile_unlock_smoke 56436273640036912925339417151157057086456427290241090475666338996601164389461 149
UVM_FATAL @ 142743253 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout lc_ctrl_regs_reg_block.status.transition_successful (addr=0x8bc24d04, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 142743253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---