Simulation Results: otbn

 
02/05/2026 09:12:14 DVSim: v1.17.3 sha: 63c8a50 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.68 %
  • code
  • 96.61 %
  • assert
  • 96.42 %
  • func
  • 100.00 %
  • block
  • 99.46 %
  • line
  • 99.62 %
  • branch
  • 93.05 %
  • toggle
  • 93.78 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
97.83%
V2S
97.35%
V3
20.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 12.000s 54.139us 1 1 100.00
single_binary 100 100 100.00
otbn_single 75.000s 320.282us 100 100 100.00
csr_hw_reset 5 5 100.00
otbn_csr_hw_reset 11.000s 58.118us 5 5 100.00
csr_rw 20 20 100.00
otbn_csr_rw 10.000s 21.904us 20 20 100.00
csr_bit_bash 5 5 100.00
otbn_csr_bit_bash 15.000s 193.006us 5 5 100.00
csr_aliasing 5 5 100.00
otbn_csr_aliasing 10.000s 55.951us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
otbn_csr_mem_rw_with_rand_reset 15.000s 39.291us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
otbn_csr_rw 10.000s 21.904us 20 20 100.00
otbn_csr_aliasing 10.000s 55.951us 5 5 100.00
mem_walk 5 5 100.00
otbn_mem_walk 118.000s 14391.805us 5 5 100.00
mem_partial_access 5 5 100.00
otbn_mem_partial_access 57.000s 1011.443us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 10 10 100.00
otbn_reset 58.000s 245.780us 10 10 100.00
multi_error 0 1 0.00
otbn_multi_err 16.361s 0.000us 0 1 0.00
back_to_back 10 10 100.00
otbn_multi 113.000s 1473.716us 10 10 100.00
stress_all 10 10 100.00
otbn_stress_all 97.000s 375.902us 10 10 100.00
lc_escalation 60 60 100.00
otbn_escalate 30.000s 110.456us 60 60 100.00
zero_state_err_urnd 0 5 0.00
otbn_zero_state_err_urnd 7.000s 13.281us 0 5 0.00
sw_errs_fatal_chk 10 10 100.00
otbn_sw_errs_fatal_chk 23.000s 92.762us 10 10 100.00
alert_test 50 50 100.00
otbn_alert_test 9.000s 33.843us 50 50 100.00
intr_test 50 50 100.00
otbn_intr_test 9.000s 13.892us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
otbn_tl_errors 14.000s 544.582us 20 20 100.00
tl_d_illegal_access 20 20 100.00
otbn_tl_errors 14.000s 544.582us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
otbn_csr_hw_reset 11.000s 58.118us 5 5 100.00
otbn_csr_rw 10.000s 21.904us 20 20 100.00
otbn_csr_aliasing 10.000s 55.951us 5 5 100.00
otbn_same_csr_outstanding 11.000s 29.935us 20 20 100.00
tl_d_partial_access 50 50 100.00
otbn_csr_hw_reset 11.000s 58.118us 5 5 100.00
otbn_csr_rw 10.000s 21.904us 20 20 100.00
otbn_csr_aliasing 10.000s 55.951us 5 5 100.00
otbn_same_csr_outstanding 11.000s 29.935us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 25 25 100.00
otbn_imem_err 12.000s 24.016us 10 10 100.00
otbn_dmem_err 15.000s 61.665us 15 15 100.00
internal_integrity 15 17 88.24
otbn_alu_bignum_mod_err 11.000s 108.924us 5 5 100.00
otbn_controller_ispr_rdata_err 9.000s 56.249us 5 5 100.00
otbn_mac_bignum_acc_err 10.000s 112.602us 5 5 100.00
otbn_urnd_err 7.000s 8.617us 0 2 0.00
illegal_bus_access 5 5 100.00
otbn_illegal_mem_acc 7.000s 23.251us 5 5 100.00
otbn_mem_gnt_acc_err 2 2 100.00
otbn_mem_gnt_acc_err 8.000s 24.213us 2 2 100.00
otbn_non_sec_partial_wipe 9 10 90.00
otbn_partial_wipe 9.000s 40.356us 9 10 90.00
tl_intg_err 25 25 100.00
otbn_tl_intg_err 47.000s 226.046us 20 20 100.00
otbn_sec_cm 206.000s 5459.301us 5 5 100.00
passthru_mem_tl_intg_err 20 20 100.00
otbn_passthru_mem_tl_intg_err 71.000s 324.859us 20 20 100.00
prim_fsm_check 5 5 100.00
otbn_sec_cm 206.000s 5459.301us 5 5 100.00
prim_count_check 5 5 100.00
otbn_sec_cm 206.000s 5459.301us 5 5 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 12.000s 54.139us 1 1 100.00
sec_cm_data_mem_integrity 15 15 100.00
otbn_dmem_err 15.000s 61.665us 15 15 100.00
sec_cm_instruction_mem_integrity 10 10 100.00
otbn_imem_err 12.000s 24.016us 10 10 100.00
sec_cm_bus_integrity 20 20 100.00
otbn_tl_intg_err 47.000s 226.046us 20 20 100.00
sec_cm_controller_fsm_global_esc 60 60 100.00
otbn_escalate 30.000s 110.456us 60 60 100.00
sec_cm_controller_fsm_local_esc 35 40 87.50
otbn_imem_err 12.000s 24.016us 10 10 100.00
otbn_dmem_err 15.000s 61.665us 15 15 100.00
otbn_zero_state_err_urnd 7.000s 13.281us 0 5 0.00
otbn_illegal_mem_acc 7.000s 23.251us 5 5 100.00
otbn_sec_cm 206.000s 5459.301us 5 5 100.00
sec_cm_controller_fsm_sparse 5 5 100.00
otbn_sec_cm 206.000s 5459.301us 5 5 100.00
sec_cm_scramble_key_sideload 100 100 100.00
otbn_single 75.000s 320.282us 100 100 100.00
sec_cm_scramble_ctrl_fsm_local_esc 35 40 87.50
otbn_imem_err 12.000s 24.016us 10 10 100.00
otbn_dmem_err 15.000s 61.665us 15 15 100.00
otbn_zero_state_err_urnd 7.000s 13.281us 0 5 0.00
otbn_illegal_mem_acc 7.000s 23.251us 5 5 100.00
otbn_sec_cm 206.000s 5459.301us 5 5 100.00
sec_cm_scramble_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 206.000s 5459.301us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 60 60 100.00
otbn_escalate 30.000s 110.456us 60 60 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 35 40 87.50
otbn_imem_err 12.000s 24.016us 10 10 100.00
otbn_dmem_err 15.000s 61.665us 15 15 100.00
otbn_zero_state_err_urnd 7.000s 13.281us 0 5 0.00
otbn_illegal_mem_acc 7.000s 23.251us 5 5 100.00
otbn_sec_cm 206.000s 5459.301us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 206.000s 5459.301us 5 5 100.00
sec_cm_data_reg_sw_sca 100 100 100.00
otbn_single 75.000s 320.282us 100 100 100.00
sec_cm_ctrl_redun 12 12 100.00
otbn_ctrl_redun 8.000s 44.758us 12 12 100.00
sec_cm_pc_ctrl_flow_redun 5 5 100.00
otbn_pc_ctrl_flow_redun 8.000s 100.086us 5 5 100.00
sec_cm_rnd_bus_consistency 5 5 100.00
otbn_rnd_sec_cm 96.000s 688.042us 5 5 100.00
sec_cm_rnd_rng_digest 5 5 100.00
otbn_rnd_sec_cm 96.000s 688.042us 5 5 100.00
sec_cm_rf_base_data_reg_sw_integrity 10 10 100.00
otbn_rf_base_intg_err 11.000s 25.546us 10 10 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 206.000s 5459.301us 5 5 100.00
sec_cm_stack_wr_ptr_ctr_redun 5 5 100.00
otbn_sec_cm 206.000s 5459.301us 5 5 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 10 10 100.00
otbn_rf_bignum_intg_err 11.000s 71.795us 10 10 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 206.000s 5459.301us 5 5 100.00
sec_cm_loop_stack_ctr_redun 5 5 100.00
otbn_sec_cm 206.000s 5459.301us 5 5 100.00
sec_cm_loop_stack_addr_integrity 4 5 80.00
otbn_stack_addr_integ_chk 112.000s 481.351us 4 5 80.00
sec_cm_call_stack_addr_integrity 4 5 80.00
otbn_stack_addr_integ_chk 112.000s 481.351us 4 5 80.00
sec_cm_start_stop_ctrl_state_consistency 7 7 100.00
otbn_sec_wipe_err 13.000s 103.924us 7 7 100.00
sec_cm_data_mem_sec_wipe 100 100 100.00
otbn_single 75.000s 320.282us 100 100 100.00
sec_cm_instruction_mem_sec_wipe 100 100 100.00
otbn_single 75.000s 320.282us 100 100 100.00
sec_cm_data_reg_sw_sec_wipe 100 100 100.00
otbn_single 75.000s 320.282us 100 100 100.00
sec_cm_write_mem_integrity 10 10 100.00
otbn_multi 113.000s 1473.716us 10 10 100.00
sec_cm_ctrl_flow_count 100 100 100.00
otbn_single 75.000s 320.282us 100 100 100.00
sec_cm_ctrl_flow_sca 100 100 100.00
otbn_single 75.000s 320.282us 100 100 100.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 39.000s 142.494us 5 5 100.00
sec_cm_key_sideload 100 100 100.00
otbn_single 75.000s 320.282us 100 100 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
otbn_sec_cm 206.000s 5459.301us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 2 10 20.00
otbn_stress_all_with_rand_reset 437.000s 1520.120us 2 10 20.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 8.000s 62.504us 1 1 100.00

Error Messages

   Test seed line log context
Job returned non-zero exit code
otbn_multi_err 82118405191549056960542481339654852079227438396295658276025529881125689294527 None
[make]: pre_run
mkdir -p /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_multi_err/latest
cd /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_multi_err/latest && pushd /nightly/current_run/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/current_run/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --src-dir /nightly/current_run/opentitan/hw/ip/otbn/dv/otbnsim/test/simple/multi /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_multi_err/latest/otbn-binaries
/nightly/current_run/opentitan /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_multi_err/latest
2026/05/02 18:58:39 Downloading https://releases.bazel.build/8.0.1/release/bazel-8.0.1-linux-x86_64...
Opening zip "/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)": open(): No such file or directory
FATAL: Failed to open '/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)' as a zip file: (error: 2): No such file or directory
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 36
UVM_ERROR (cip_base_vseq.sv:1237) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
otbn_stress_all_with_rand_reset 67983325260029218530457002344405667640924059630018676356688662487438838954017 457
UVM_ERROR @ 1564054502 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1564054502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 35229680856110214578334637541557514780695198851639494972473944346241458639172 330
UVM_ERROR @ 6332462689 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 6332462689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 90193077125861982128795263453170857727035672410496805243599650337802246519185 409
UVM_ERROR @ 2251159878 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2251159878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.u_otbn_core.u_otbn_rnd.u_xoshiro256pp.xoshiro_q cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
otbn_zero_state_err_urnd 72087710999534108410017122236305818047671577251478368436462635890908076858740 110
UVM_ERROR @ 3602407 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.u_otbn_core.u_otbn_rnd.u_xoshiro256pp.xoshiro_q cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_INFO @ 3602407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_zero_state_err_urnd 54244717955849328024175013231973880486513885783659142200085957731962221329362 108
UVM_ERROR @ 12309736 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.u_otbn_core.u_otbn_rnd.u_xoshiro256pp.xoshiro_q cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_INFO @ 12309736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_zero_state_err_urnd 112096384625545161891030071058914807928578255272871386753909229252856532025794 108
UVM_ERROR @ 9319344 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.u_otbn_core.u_otbn_rnd.u_xoshiro256pp.xoshiro_q cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_INFO @ 9319344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_zero_state_err_urnd 63786385472530936013869693316725767131502956196827513962561277383673621176307 107
UVM_ERROR @ 5534511 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.u_otbn_core.u_otbn_rnd.u_xoshiro256pp.xoshiro_q cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_INFO @ 5534511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_zero_state_err_urnd 95516105122467130261004979379192438057705633837024977338985853430253520818746 105
UVM_ERROR @ 13280872 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.u_otbn_core.u_otbn_rnd.u_xoshiro256pp.xoshiro_q cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_INFO @ 13280872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.edn_urnd_ack cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
otbn_urnd_err 23659116310423296792772862517302389341322968793459619730356830627330882221792 139
UVM_ERROR @ 8616588 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.edn_urnd_ack cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_INFO @ 8616588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_urnd_err 77761606440113758400183697247892783033162700993634373216168826310925353952794 103
UVM_ERROR @ 12004785 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.edn_urnd_ack cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_INFO @ 12004785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
otbn_stress_all_with_rand_reset 51588719709447301518088834697385988424528328475962764906865650689495484473000 167
UVM_FATAL @ 33334976 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 33334976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 9799517188926159092309017818875999983525815177318295686384974327627002216126 580
UVM_FATAL @ 1520120483 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 1520120483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 109382802895989725640000156866299384994355106211543977847884961713334308183447 196
UVM_FATAL @ 900356699 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 900356699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed
otbn_stack_addr_integ_chk 287958912463807140035673743255838027928436880838715059548303571453561607481 120
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 20638909 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 20638909 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 20638909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset)
otbn_stress_all_with_rand_reset 83217679958360064266519538448384358064950061518967297286763706939474279396970 157
UVM_FATAL @ 27508164 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 27508164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sim_*/tb.sv,292): Assertion MatchingStatus_A has failed
otbn_partial_wipe 55417952302197151411509698944989813657946206759635238118813151186034263121725 108
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sim_0.1/tb.sv,292): (time 32530762 PS) Assertion tb.MatchingStatus_A has failed
UVM_ERROR @ 32530762 ps: (tb.sv:292) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 32530762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1028) virtual_sequencer [otbn_imem_err_vseq] expect alert:fatal to fire
otbn_stress_all_with_rand_reset 62209915615688811167702714403074888917680721431526803040399110906215910688716 440
UVM_ERROR @ 2288180025 ps: (cip_base_vseq.sv:1028) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] expect alert:fatal to fire
UVM_INFO @ 2288180025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---