| V1 |
|
94.83% |
| V2 |
|
90.89% |
| V2S |
|
88.65% |
| V3 |
|
18.81% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| wake_up | 1 | 1 | 100.00 | |||
| otp_ctrl_wake_up | 2.440s | 106.201us | 1 | 1 | 100.00 | |
| smoke | 50 | 50 | 100.00 | |||
| otp_ctrl_smoke | 15.130s | 4225.711us | 50 | 50 | 100.00 | |
| csr_hw_reset | 5 | 5 | 100.00 | |||
| otp_ctrl_csr_hw_reset | 3.180s | 1024.142us | 5 | 5 | 100.00 | |
| csr_rw | 20 | 20 | 100.00 | |||
| otp_ctrl_csr_rw | 2.260s | 655.026us | 20 | 20 | 100.00 | |
| csr_bit_bash | 5 | 5 | 100.00 | |||
| otp_ctrl_csr_bit_bash | 6.360s | 430.648us | 5 | 5 | 100.00 | |
| csr_aliasing | 5 | 5 | 100.00 | |||
| otp_ctrl_csr_aliasing | 3.700s | 454.647us | 5 | 5 | 100.00 | |
| csr_mem_rw_with_rand_reset | 14 | 20 | 70.00 | |||
| otp_ctrl_csr_mem_rw_with_rand_reset | 3.030s | 927.463us | 14 | 20 | 70.00 | |
| regwen_csr_and_corresponding_lockable_csr | 25 | 25 | 100.00 | |||
| otp_ctrl_csr_rw | 2.260s | 655.026us | 20 | 20 | 100.00 | |
| otp_ctrl_csr_aliasing | 3.700s | 454.647us | 5 | 5 | 100.00 | |
| mem_walk | 5 | 5 | 100.00 | |||
| otp_ctrl_mem_walk | 1.730s | 499.974us | 5 | 5 | 100.00 | |
| mem_partial_access | 5 | 5 | 100.00 | |||
| otp_ctrl_mem_partial_access | 1.230s | 138.703us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| dai_access_partition_walk | 1 | 1 | 100.00 | |||
| otp_ctrl_partition_walk | 20.060s | 3084.787us | 1 | 1 | 100.00 | |
| init_fail | 281 | 300 | 93.67 | |||
| otp_ctrl_init_fail | 6.780s | 2129.876us | 281 | 300 | 93.67 | |
| partition_check | 21 | 60 | 35.00 | |||
| otp_ctrl_background_chks | 34.740s | 14199.450us | 8 | 10 | 80.00 | |
| otp_ctrl_check_fail | 22.370s | 1472.247us | 13 | 50 | 26.00 | |
| regwen_during_otp_init | 50 | 50 | 100.00 | |||
| otp_ctrl_regwen | 12.080s | 1272.962us | 50 | 50 | 100.00 | |
| partition_lock | 50 | 50 | 100.00 | |||
| otp_ctrl_dai_lock | 48.390s | 6940.584us | 50 | 50 | 100.00 | |
| interface_key_check | 50 | 50 | 100.00 | |||
| otp_ctrl_parallel_key_req | 40.730s | 3935.217us | 50 | 50 | 100.00 | |
| lc_interactions | 250 | 250 | 100.00 | |||
| otp_ctrl_parallel_lc_req | 32.620s | 13468.928us | 50 | 50 | 100.00 | |
| otp_ctrl_parallel_lc_esc | 28.430s | 11286.575us | 200 | 200 | 100.00 | |
| otp_dai_errors | 48 | 50 | 96.00 | |||
| otp_ctrl_dai_errs | 74.310s | 25878.417us | 48 | 50 | 96.00 | |
| otp_macro_errors | 18 | 50 | 36.00 | |||
| otp_ctrl_macro_errs | 40.250s | 3863.588us | 18 | 50 | 36.00 | |
| test_access | 50 | 50 | 100.00 | |||
| otp_ctrl_test_access | 66.330s | 31941.796us | 50 | 50 | 100.00 | |
| stress_all | 39 | 50 | 78.00 | |||
| otp_ctrl_stress_all | 360.720s | 139893.026us | 39 | 50 | 78.00 | |
| intr_test | 50 | 50 | 100.00 | |||
| otp_ctrl_intr_test | 1.870s | 518.552us | 50 | 50 | 100.00 | |
| alert_test | 50 | 50 | 100.00 | |||
| otp_ctrl_alert_test | 7.850s | 592.944us | 50 | 50 | 100.00 | |
| tl_d_oob_addr_access | 20 | 20 | 100.00 | |||
| otp_ctrl_tl_errors | 6.320s | 2476.316us | 20 | 20 | 100.00 | |
| tl_d_illegal_access | 20 | 20 | 100.00 | |||
| otp_ctrl_tl_errors | 6.320s | 2476.316us | 20 | 20 | 100.00 | |
| tl_d_outstanding_access | 50 | 50 | 100.00 | |||
| otp_ctrl_csr_hw_reset | 3.180s | 1024.142us | 5 | 5 | 100.00 | |
| otp_ctrl_csr_rw | 2.260s | 655.026us | 20 | 20 | 100.00 | |
| otp_ctrl_csr_aliasing | 3.700s | 454.647us | 5 | 5 | 100.00 | |
| otp_ctrl_same_csr_outstanding | 4.890s | 2326.080us | 20 | 20 | 100.00 | |
| tl_d_partial_access | 50 | 50 | 100.00 | |||
| otp_ctrl_csr_hw_reset | 3.180s | 1024.142us | 5 | 5 | 100.00 | |
| otp_ctrl_csr_rw | 2.260s | 655.026us | 20 | 20 | 100.00 | |
| otp_ctrl_csr_aliasing | 3.700s | 454.647us | 5 | 5 | 100.00 | |
| otp_ctrl_same_csr_outstanding | 4.890s | 2326.080us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| sec_cm_additional_check | 5 | 5 | 100.00 | |||
| otp_ctrl_sec_cm | 147.750s | 43124.019us | 5 | 5 | 100.00 | |
| tl_intg_err | 25 | 25 | 100.00 | |||
| otp_ctrl_sec_cm | 147.750s | 43124.019us | 5 | 5 | 100.00 | |
| otp_ctrl_tl_intg_err | 15.810s | 5070.804us | 20 | 20 | 100.00 | |
| prim_count_check | 5 | 5 | 100.00 | |||
| otp_ctrl_sec_cm | 147.750s | 43124.019us | 5 | 5 | 100.00 | |
| prim_fsm_check | 5 | 5 | 100.00 | |||
| otp_ctrl_sec_cm | 147.750s | 43124.019us | 5 | 5 | 100.00 | |
| sec_cm_bus_integrity | 20 | 20 | 100.00 | |||
| otp_ctrl_tl_intg_err | 15.810s | 5070.804us | 20 | 20 | 100.00 | |
| sec_cm_secret_mem_scramble | 50 | 50 | 100.00 | |||
| otp_ctrl_smoke | 15.130s | 4225.711us | 50 | 50 | 100.00 | |
| sec_cm_part_mem_digest | 50 | 50 | 100.00 | |||
| otp_ctrl_smoke | 15.130s | 4225.711us | 50 | 50 | 100.00 | |
| sec_cm_dai_fsm_sparse | 5 | 5 | 100.00 | |||
| otp_ctrl_sec_cm | 147.750s | 43124.019us | 5 | 5 | 100.00 | |
| sec_cm_kdi_fsm_sparse | 5 | 5 | 100.00 | |||
| otp_ctrl_sec_cm | 147.750s | 43124.019us | 5 | 5 | 100.00 | |
| sec_cm_lci_fsm_sparse | 5 | 5 | 100.00 | |||
| otp_ctrl_sec_cm | 147.750s | 43124.019us | 5 | 5 | 100.00 | |
| sec_cm_part_fsm_sparse | 5 | 5 | 100.00 | |||
| otp_ctrl_sec_cm | 147.750s | 43124.019us | 5 | 5 | 100.00 | |
| sec_cm_scrmbl_fsm_sparse | 5 | 5 | 100.00 | |||
| otp_ctrl_sec_cm | 147.750s | 43124.019us | 5 | 5 | 100.00 | |
| sec_cm_timer_fsm_sparse | 5 | 5 | 100.00 | |||
| otp_ctrl_sec_cm | 147.750s | 43124.019us | 5 | 5 | 100.00 | |
| sec_cm_dai_ctr_redun | 5 | 5 | 100.00 | |||
| otp_ctrl_sec_cm | 147.750s | 43124.019us | 5 | 5 | 100.00 | |
| sec_cm_kdi_seed_ctr_redun | 5 | 5 | 100.00 | |||
| otp_ctrl_sec_cm | 147.750s | 43124.019us | 5 | 5 | 100.00 | |
| sec_cm_kdi_entropy_ctr_redun | 5 | 5 | 100.00 | |||
| otp_ctrl_sec_cm | 147.750s | 43124.019us | 5 | 5 | 100.00 | |
| sec_cm_lci_ctr_redun | 5 | 5 | 100.00 | |||
| otp_ctrl_sec_cm | 147.750s | 43124.019us | 5 | 5 | 100.00 | |
| sec_cm_part_ctr_redun | 5 | 5 | 100.00 | |||
| otp_ctrl_sec_cm | 147.750s | 43124.019us | 5 | 5 | 100.00 | |
| sec_cm_scrmbl_ctr_redun | 5 | 5 | 100.00 | |||
| otp_ctrl_sec_cm | 147.750s | 43124.019us | 5 | 5 | 100.00 | |
| sec_cm_timer_integ_ctr_redun | 5 | 5 | 100.00 | |||
| otp_ctrl_sec_cm | 147.750s | 43124.019us | 5 | 5 | 100.00 | |
| sec_cm_timer_cnsty_ctr_redun | 5 | 5 | 100.00 | |||
| otp_ctrl_sec_cm | 147.750s | 43124.019us | 5 | 5 | 100.00 | |
| sec_cm_timer_lfsr_redun | 5 | 5 | 100.00 | |||
| otp_ctrl_sec_cm | 147.750s | 43124.019us | 5 | 5 | 100.00 | |
| sec_cm_dai_fsm_local_esc | 205 | 205 | 100.00 | |||
| otp_ctrl_parallel_lc_esc | 28.430s | 11286.575us | 200 | 200 | 100.00 | |
| otp_ctrl_sec_cm | 147.750s | 43124.019us | 5 | 5 | 100.00 | |
| sec_cm_lci_fsm_local_esc | 200 | 200 | 100.00 | |||
| otp_ctrl_parallel_lc_esc | 28.430s | 11286.575us | 200 | 200 | 100.00 | |
| sec_cm_kdi_fsm_local_esc | 200 | 200 | 100.00 | |||
| otp_ctrl_parallel_lc_esc | 28.430s | 11286.575us | 200 | 200 | 100.00 | |
| sec_cm_part_fsm_local_esc | 218 | 250 | 87.20 | |||
| otp_ctrl_parallel_lc_esc | 28.430s | 11286.575us | 200 | 200 | 100.00 | |
| otp_ctrl_macro_errs | 40.250s | 3863.588us | 18 | 50 | 36.00 | |
| sec_cm_scrmbl_fsm_local_esc | 200 | 200 | 100.00 | |||
| otp_ctrl_parallel_lc_esc | 28.430s | 11286.575us | 200 | 200 | 100.00 | |
| sec_cm_timer_fsm_local_esc | 205 | 205 | 100.00 | |||
| otp_ctrl_parallel_lc_esc | 28.430s | 11286.575us | 200 | 200 | 100.00 | |
| otp_ctrl_sec_cm | 147.750s | 43124.019us | 5 | 5 | 100.00 | |
| sec_cm_dai_fsm_global_esc | 205 | 205 | 100.00 | |||
| otp_ctrl_parallel_lc_esc | 28.430s | 11286.575us | 200 | 200 | 100.00 | |
| otp_ctrl_sec_cm | 147.750s | 43124.019us | 5 | 5 | 100.00 | |
| sec_cm_lci_fsm_global_esc | 200 | 200 | 100.00 | |||
| otp_ctrl_parallel_lc_esc | 28.430s | 11286.575us | 200 | 200 | 100.00 | |
| sec_cm_kdi_fsm_global_esc | 200 | 200 | 100.00 | |||
| otp_ctrl_parallel_lc_esc | 28.430s | 11286.575us | 200 | 200 | 100.00 | |
| sec_cm_part_fsm_global_esc | 218 | 250 | 87.20 | |||
| otp_ctrl_parallel_lc_esc | 28.430s | 11286.575us | 200 | 200 | 100.00 | |
| otp_ctrl_macro_errs | 40.250s | 3863.588us | 18 | 50 | 36.00 | |
| sec_cm_scrmbl_fsm_global_esc | 200 | 200 | 100.00 | |||
| otp_ctrl_parallel_lc_esc | 28.430s | 11286.575us | 200 | 200 | 100.00 | |
| sec_cm_timer_fsm_global_esc | 205 | 205 | 100.00 | |||
| otp_ctrl_parallel_lc_esc | 28.430s | 11286.575us | 200 | 200 | 100.00 | |
| otp_ctrl_sec_cm | 147.750s | 43124.019us | 5 | 5 | 100.00 | |
| sec_cm_part_data_reg_integrity | 281 | 300 | 93.67 | |||
| otp_ctrl_init_fail | 6.780s | 2129.876us | 281 | 300 | 93.67 | |
| sec_cm_part_data_reg_bkgn_chk | 13 | 50 | 26.00 | |||
| otp_ctrl_check_fail | 22.370s | 1472.247us | 13 | 50 | 26.00 | |
| sec_cm_part_mem_regren | 50 | 50 | 100.00 | |||
| otp_ctrl_dai_lock | 48.390s | 6940.584us | 50 | 50 | 100.00 | |
| sec_cm_part_mem_sw_unreadable | 50 | 50 | 100.00 | |||
| otp_ctrl_dai_lock | 48.390s | 6940.584us | 50 | 50 | 100.00 | |
| sec_cm_part_mem_sw_unwritable | 50 | 50 | 100.00 | |||
| otp_ctrl_dai_lock | 48.390s | 6940.584us | 50 | 50 | 100.00 | |
| sec_cm_lc_part_mem_sw_noaccess | 50 | 50 | 100.00 | |||
| otp_ctrl_dai_lock | 48.390s | 6940.584us | 50 | 50 | 100.00 | |
| sec_cm_access_ctrl_mubi | 50 | 50 | 100.00 | |||
| otp_ctrl_dai_lock | 48.390s | 6940.584us | 50 | 50 | 100.00 | |
| sec_cm_token_valid_ctrl_mubi | 50 | 50 | 100.00 | |||
| otp_ctrl_smoke | 15.130s | 4225.711us | 50 | 50 | 100.00 | |
| sec_cm_lc_ctrl_intersig_mubi | 50 | 50 | 100.00 | |||
| otp_ctrl_dai_lock | 48.390s | 6940.584us | 50 | 50 | 100.00 | |
| sec_cm_test_bus_lc_gated | 50 | 50 | 100.00 | |||
| otp_ctrl_smoke | 15.130s | 4225.711us | 50 | 50 | 100.00 | |
| sec_cm_test_tl_lc_gate_fsm_sparse | 5 | 5 | 100.00 | |||
| otp_ctrl_sec_cm | 147.750s | 43124.019us | 5 | 5 | 100.00 | |
| sec_cm_direct_access_config_regwen | 50 | 50 | 100.00 | |||
| otp_ctrl_regwen | 12.080s | 1272.962us | 50 | 50 | 100.00 | |
| sec_cm_check_trigger_config_regwen | 50 | 50 | 100.00 | |||
| otp_ctrl_smoke | 15.130s | 4225.711us | 50 | 50 | 100.00 | |
| sec_cm_check_config_regwen | 50 | 50 | 100.00 | |||
| otp_ctrl_smoke | 15.130s | 4225.711us | 50 | 50 | 100.00 | |
| sec_cm_macro_mem_integrity | 18 | 50 | 36.00 | |||
| otp_ctrl_macro_errs | 40.250s | 3863.588us | 18 | 50 | 36.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| otp_ctrl_low_freq_read | 1 | 1 | 100.00 | |||
| otp_ctrl_low_freq_read | 17.100s | 6927.951us | 1 | 1 | 100.00 | |
| stress_all_with_rand_reset | 18 | 100 | 18.00 | |||
| otp_ctrl_stress_all_with_rand_reset | 221.700s | 91697.623us | 18 | 100 | 18.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (cip_base_vseq.sv:1315) [otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_check_error does not trigger! | ||||
| otp_ctrl_background_chks | 10346499657703360512076828663472922029689259460915267997811018128623601069954 | 9292 |
UVM_ERROR @ 3281893055 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 3281893055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 112308656568489144913523183086047947694094234930049521857333420062461985172596 | 37236 |
UVM_ERROR @ 15398113507 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 15398113507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 21199962518310730224446319558211884662539113650236356515671605266436144855132 | 31502 |
UVM_ERROR @ 4295598234 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 4295598234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_background_chks | 37098453980631725986851925556594086436548514410832055731970249459654715136974 | 2521 |
UVM_ERROR @ 1225866356 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 1225866356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 65462740093850023662680999683807091163138491785921968623833605287736780471220 | 108594 |
UVM_ERROR @ 43774941909 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 43774941909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 6350768581023605077756356850617486089742983968533554378684638634916580043090 | 77376 |
UVM_ERROR @ 4614410901 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 4614410901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 111914693735186759229376600664929500250108290325705587305299522867607493651992 | 8996 |
UVM_ERROR @ 12815730080 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 12815730080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 109527316088811437766009687710734566037921559793364740980776098924734956936008 | 8805 |
UVM_ERROR @ 792578647 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 792578647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 13142662656462959153932718339612631736378981002276090191846709291140300788797 | 97993 |
UVM_ERROR @ 10292284304 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 10292284304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 60819748305779040595210585136144496973241527956585448332193474877213524813990 | 17752 |
UVM_ERROR @ 31387679298 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 31387679298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 11627301350933841153749289460136327175955443693275563669009714927419278424197 | 14436 |
UVM_ERROR @ 6168845711 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 6168845711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 102741772118574185295868185273334155058789407462353506994076421572165711024814 | 11206 |
UVM_ERROR @ 981997927 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 981997927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 88233583676525532867184698322019925746718880133160388124007630572505433723812 | 10626 |
UVM_ERROR @ 1798470000 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 1798470000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 37571516836869373193368041794967576297781744322377979143816176446465144870708 | 15776 |
UVM_ERROR @ 1350963954 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 1350963954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 93252562047733475198882036127164192593135431184875370296323606474659332071258 | 5672 |
UVM_ERROR @ 814311235 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 814311235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 106499714675524922685773923329514866831286931024121406818358939488048163743393 | 1101 |
UVM_ERROR @ 1023170277 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 1023170277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* | ||||
| otp_ctrl_check_fail | 66109164299105155459794133495801805695366885749819498465160907026569518938181 | 15262 |
UVM_ERROR @ 1785403027 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1801018254 [0x6b595b8e] vs 1801018255 [0x6b595b8f]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 1785403027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 101732222296835689148255025345700810407690619071469216421449601388443109589076 | 863 |
UVM_ERROR @ 82251538 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 256 [0x100]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 82251538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 64970434829191086305605311917818607185854588526298118697692534353635141638000 | 20074 |
UVM_ERROR @ 2334595704 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2048 [0x800]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 2334595704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 98574418355764602082879692319109363738761767001014593255488393039654448076888 | 9954 |
UVM_ERROR @ 9687970295 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2647648672 [0x9dcfe9a0] vs 2647615904 [0x9dcf69a0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 9687970295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 15954541317079735171279812770835729143604565088914408923146754229639456803822 | 19146 |
UVM_ERROR @ 566675977 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 128 [0x80]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 566675977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 111396234320433693016054277489367369699997468062602406292713576629214077256005 | 2398 |
UVM_ERROR @ 345929313 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2 [0x2]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 345929313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 73844202589913851861517989474271665519903109980527705819339449882788488204189 | 2701 |
UVM_ERROR @ 339723883 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 10 [0xa]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 339723883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 24466909966829932585255579629216027479809823572723350293755863668770318617938 | 1876 |
UVM_ERROR @ 3905860889 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4190466362 [0xf9c5713a] vs 4190466354 [0xf9c57132]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 3905860889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 68361342210778875834774015753784539816019482689592807735700831133018895425637 | 4744 |
UVM_ERROR @ 2224356447 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 32768 [0x8000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 2224356447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 83026192768527233223150559571141190756781838619309202647437999595379910470371 | 1977 |
UVM_ERROR @ 428509663 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 32768 [0x8000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 428509663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 106782271797904926294613799440085371611643391400245842327223284534419433266864 | 2008 |
UVM_ERROR @ 620844848 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 256 [0x100]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 620844848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 92869783029338945215170767233902905212726570664363630290707665115031153354431 | 501 |
UVM_ERROR @ 961470014 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3268733106 [0xc2d4e8b2] vs 3268733107 [0xc2d4e8b3]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 961470014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 55384287417983229788817942569807422548008790456258704085946291977827877047532 | 1041 |
UVM_ERROR @ 1020940433 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (472332086 [0x1c273736] vs 472332070 [0x1c273726]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 1020940433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 28055053671724554300923748902081155527242260398967613656595133624472155722187 | 3023 |
UVM_ERROR @ 335602962 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 8193 [0x2001]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 335602962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 6251625538384783870170991093927763357088553910023353821727672445000864071281 | 1009 |
UVM_ERROR @ 263584831 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3048362512 [0xb5b25210] vs 3048363536 [0xb5b25610]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 263584831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 109233969011035864919939244208941074880890043729738040019271870881282183852336 | 3308 |
UVM_ERROR @ 324188132 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 324188132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 61146575444725941029518226238926775159859679467860440705219430886237522667800 | 6538 |
UVM_ERROR @ 3072120292 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2219240610 [0x8446eca2] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 3072120292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 30924738225538572489582932036407433740189587181750192617472098152692028238763 | 211 |
UVM_ERROR @ 125710039 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4259936493 [0xfde978ed] vs 4259935469 [0xfde974ed]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 125710039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 33176632993518488532548348272832366365060525899162492184183056600846899847994 | 2788 |
UVM_ERROR @ 255927479 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 16 [0x10]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 255927479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 103354333957651379778889372842734882332138510500303932561328610236233406323085 | 19136 |
UVM_ERROR @ 2421129777 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1702639062 [0x657c35d6] vs 1837086206 [0x6d7fb5fe]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 2421129777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 24990268352898357229231417979433006343817427556598075780406832235320725389110 | 1779 |
UVM_ERROR @ 623366427 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 64 [0x40]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 623366427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 29927172514902524163807678827478460311300135880384341944492046754370199438067 | 627 |
UVM_ERROR @ 102541956 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 4096 [0x1000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 102541956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_dai_errs | 37682626782950912307319006655169319776911802428338147320850608971841150503036 | 3115 |
UVM_ERROR @ 91554883 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (149735442 [0x8ecc812] vs 268303675 [0xffdfd3b]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 91554883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 533416337206064049588817100531028171537047100539996917294473858462757014158 | 151 |
UVM_ERROR @ 776008551 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1535435603 [0x5b84e353] vs 1535435607 [0x5b84e357]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 776008551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 95708746353799287033015533863361998197428782384827477721215182581711614455514 | 6128 |
UVM_ERROR @ 520780115 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 32768 [0x8000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 520780115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 30147138568800592962049605485165075237950952257252676790252617669270792753924 | 2041 |
UVM_ERROR @ 523938897 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 512 [0x200]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 523938897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 24845246704753951846733417140368207723884572843564652921042759107544032752229 | 1685 |
UVM_ERROR @ 136666653 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 128 [0x80]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 136666653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 82132118048245090847059707470929832611567257562265103272713981836260893296395 | 8180 |
UVM_ERROR @ 556106810 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 8 [0x8]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 556106810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 109738046149207684707661613225213422762922935758112808687764301298325747828477 | 401 |
UVM_ERROR @ 500976013 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 4 [0x4]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 500976013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 63120608883290214913239585371483799304592936769752590695042849403719632059626 | 171 |
UVM_ERROR @ 90283137 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 4096 [0x1000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 90283137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 74428940352061571508821951182809540371013837047678727514449444163558870668894 | 583 |
UVM_ERROR @ 1139706741 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 256 [0x100]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 1139706741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 28944582351788494407275736450496434798153463119483176434079040134243064583222 | 1065 |
UVM_ERROR @ 1471670116 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3973978735 [0xecde1a6f] vs 3973976687 [0xecde126f]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 1471670116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_dai_errs | 79179812272597913245682287797442838512488620287648814856302560691099011206335 | 1069 |
UVM_ERROR @ 73254960 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1627230320 [0x60fd9070] vs 3909073528 [0xe8ffba78]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 73254960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 27341796106176249234768428084022599826757875162179172371872700768130254304702 | 8163 |
UVM_ERROR @ 487745958 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 4 [0x4]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 487745958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 70060907805366315547778942462386058737573895218766838411910337893071770077561 | 3726 |
UVM_ERROR @ 621616943 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 64 [0x40]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 621616943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 64307937309511540675992045082936655903813987813430147697635986959829859242677 | 2753 |
UVM_ERROR @ 739997123 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 32768 [0x8000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 739997123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 3053114269254725642308443323412735920377821058374787614778326619010246131710 | 829 |
UVM_ERROR @ 1384201166 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (551435856 [0x20de3e50] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 1384201166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 102657847475145651981674215194684042456610566070716585506365439440772734237342 | 4636 |
UVM_ERROR @ 427993679 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 16384 [0x4000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 427993679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 84926280043603285595775218450290505555829837275889780771785003752488332113962 | 725 |
UVM_ERROR @ 199319061 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (33712427 [0x202692b] vs 33687851 [0x202092b]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 199319061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 9819477892868087578487485131781669902343619360839317771663888011359175738299 | 821 |
UVM_ERROR @ 66065293 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 64 [0x40]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 66065293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 29808973993123901256327023014941322384735873187051409599770837304868136770266 | 2243 |
UVM_ERROR @ 197648298 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3911929480 [0xe92b4e88] vs 3911928968 [0xe92b4c88]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 197648298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 266892395695667381600435827178746198445265282667397594492123572883587172299 | 223 |
UVM_ERROR @ 269465714 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1886291611 [0x706e869b] vs 1886291615 [0x706e869f]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 269465714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 113670440360905157496048569258116063659658880098161268384906255952555558233695 | 2316 |
UVM_ERROR @ 328695074 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 64 [0x40]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 328695074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 45634999442094621329067505120305853136987271621297892805684930163247388042341 | 1868 |
UVM_ERROR @ 144135197 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3797776315 [0xe25d77bb] vs 3797776307 [0xe25d77b3]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 144135197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 17986981124643887201984250267329231096871272331985602556070700917684437124239 | 559 |
UVM_ERROR @ 572973586 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 8192 [0x2000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 572973586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 105754002181687797470855017553927142461943874834358124274983770414129364090156 | 2683 |
UVM_ERROR @ 455373415 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 512 [0x200]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 455373415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 73937880659903298214027700480734544491367163794673807090960510898158451087890 | 5503 |
UVM_ERROR @ 7333795462 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 4 [0x4]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 7333795462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 72240339995461397431066161365956584903059326487283480576847797112216325868599 | 829 |
UVM_ERROR @ 1304018014 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 128 [0x80]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 1304018014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 20436341904000562114257537857359164787936466126030942978534568070880179747704 | 6003 |
UVM_ERROR @ 5850727045 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 4096 [0x1000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 5850727045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 95432667560159223248681631888067720904414115287330744126048626343157327725972 | 295 |
UVM_ERROR @ 137141021 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2713282238 [0xa1b966be] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 137141021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 71799429485835833176658145232265720559584969427027508213520822282128767421121 | 409 |
UVM_ERROR @ 71080750 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 4 [0x4]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 71080750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 64474685456931463895093891012451795014848407805831969719190345711655050642705 | 173 |
UVM_ERROR @ 71967268 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1150124124 [0x448d805c] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 71967268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all | 44613168552515866846339095016003405035603045698036330342032128430269274321328 | 95064 |
UVM_ERROR @ 12410700019 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2535099144 [0x971a8b08] vs 3745418174 [0xdf3e8bbe]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 12410700019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 72855857581833466139438174278491451603741973064249399180108265440698517089925 | 4045 |
UVM_ERROR @ 209636456 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 16384 [0x4000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 209636456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 26328348623123205284714073651872390353516225315128776320844079227441312907339 | 4887 |
UVM_ERROR @ 642823594 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 8192 [0x2000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 642823594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 36369336917973104884630696181405848222741401564990164088730686440668026062655 | 10229 |
UVM_ERROR @ 518049551 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 514 [0x202]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 518049551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 68070176330062421021850650442302977273006425468635819095280109811250992066309 | 3333 |
UVM_ERROR @ 908108311 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3202814327 [0xbee71177] vs 3202822519 [0xbee73177]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 908108311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 18494806148891173754900062207235651609289533974050087050450188226880558333554 | 4607 |
UVM_ERROR @ 296042039 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 32768 [0x8000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 296042039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 8185410979101585182168526326058827539940986600723017831642428926497793277939 | 215 |
UVM_ERROR @ 117199129 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 34816 [0x8800]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 117199129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 25823814193826825168157815427026305595745572102801300033515961942636664115670 | 8474 |
UVM_ERROR @ 1509879799 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 128 [0x80]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 1509879799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 75562778285363767793469696121809543168261175461671542603288706070953806808117 | 6868 |
UVM_ERROR @ 1672523800 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (47746735 [0x2d88eaf] vs 47745711 [0x2d88aaf]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 1672523800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 58609570705736626294902616152910293628502442787873353669148311899310418833612 | 3538 |
UVM_ERROR @ 578917368 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 4096 [0x1000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 578917368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 86012088754934828441558398774732723215424611263812100847778679659711722386260 | 1847 |
UVM_ERROR @ 124935322 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 64 [0x40]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 124935322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 84034893206394884922312048889721782980112534070759626180306121719303732064952 | 6749 |
UVM_ERROR @ 974267631 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (113780082 [0x6c82572] vs 113780083 [0x6c82573]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 974267631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 35021020615512985655781785801941899451084381048779283113035115218579451310624 | 637 |
UVM_ERROR @ 225526241 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 16 [0x10]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 225526241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 74325131878391300129556836486563641460510580688126621933904866991275981344411 | 6743 |
UVM_ERROR @ 508208601 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 16 [0x10]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 508208601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 86123309105386996599467244985291027292708024209880041325247653395441373215636 | 843 |
UVM_ERROR @ 227639765 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 4 [0x4]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 227639765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 59834781997075086705506218850464134731391278001651403700295791888947936615215 | 32530 |
UVM_ERROR @ 65822653562 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2306038489 [0x89735ad9] vs 2415385567 [0x8ff7dbdf]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 65822653562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 30786957584204955497925488538299030371149781382061862220154765319959983019360 | 192 |
UVM_ERROR @ 198955319 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2851286309 [0xa9f32d25] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 198955319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 81490686368620768011014587567056206279789584187959227076332046053490535485585 | 4674 |
UVM_ERROR @ 3482280126 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (264027487 [0xfbcbd5f] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 3482280126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 6786099948119830518601140769368299789696266203521851046662889556860659079546 | 4173 |
UVM_ERROR @ 357157407 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2705093568 [0xa13c73c0] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 357157407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 2206393275827464343790746410306781024431610180626702884970751408998313922069 | 1925 |
UVM_ERROR @ 14369978298 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 494532538 [0x1d79f7ba]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 14369978298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state | ||||
| otp_ctrl_stress_all_with_rand_reset | 114406561080655976225647397793014916161528984708669540634217093938168594030134 | 225 |
UVM_ERROR @ 98279274 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
UVM_INFO @ 98279274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 2982660400787287707346069410926778839923767461186402275452509618364982588378 | 607 |
UVM_ERROR @ 186720157 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
UVM_INFO @ 186720157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 59227603620830279282388791050984468353003444558393235772270884926262820596727 | 339 |
UVM_ERROR @ 1579701628 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
UVM_INFO @ 1579701628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_check_fail | 34236042451702570515366020781687825467126762968035155342591120485422065401153 | 403 |
UVM_ERROR @ 76023235 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3 [0x3] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
UVM_INFO @ 76023235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 99599210920115107999976781133621027734058871452634226189235317126903567863806 | 147 |
UVM_ERROR @ 75822947 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
UVM_INFO @ 75822947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 82540049056647388815980065032862285050414758711055447566480153862387036642630 | 2800 |
UVM_ERROR @ 2344208048 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
UVM_INFO @ 2344208048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 27573492782566257002887468962556701468702176509221213741685644183991572265164 | 5210 |
UVM_ERROR @ 1574543717 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
UVM_INFO @ 1574543717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 97374302347088552708743594656514294338940087360673995524760687902963441640297 | 15960 |
UVM_ERROR @ 5233638275 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
UVM_INFO @ 5233638275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 52533429860241689699273385996801703617679224317232156431762989426811050991360 | 7532 |
UVM_ERROR @ 18323340355 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
UVM_INFO @ 18323340355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 89604871478356053302845433569724396852442446086139918497632551685780085180809 | 56940 |
UVM_ERROR @ 91697622561 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
UVM_INFO @ 91697622561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 42438902401999796453168676597006733346788328378636546390342339296965550251836 | 11378 |
UVM_ERROR @ 1051060764 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
UVM_INFO @ 1051060764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 81033185126423785020854637680034192542800915479575538314884104757781290862616 | 804 |
UVM_ERROR @ 148973706 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.intr_state
UVM_INFO @ 148973706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 22452751654976525951436561159980463925106895811847179584664652392777394235025 | 8132 |
UVM_ERROR @ 3152149773 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
UVM_INFO @ 3152149773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (otp_ctrl_scoreboard.sv:1825) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * | ||||
| otp_ctrl_stress_all_with_rand_reset | 100587058755123439218969854991723763797797435537231632721427606686378584304328 | 92 |
UVM_ERROR @ 429552944 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 429552944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 51159150333750263281930101658502495060582350823229851377975002227815091688363 | 92 |
UVM_ERROR @ 26715163 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 26715163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 113422397656153491805521082329401120403376269718594743577304751115780995344351 | 600 |
UVM_ERROR @ 2364989205 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 2364989205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 86096834827609894081758095659475781559452502713186861625179552823099677572340 | 47462 |
UVM_ERROR @ 2180419206 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 2180419206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 64637737882962668770064002116575989504084683518322947286452905000886166161705 | 92 |
UVM_ERROR @ 27063315 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 27063315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 47025018466037446775975433616689633766235432578559775521482369347897047691070 | 92 |
UVM_ERROR @ 26835229 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 26835229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 77222844954738767572267544013086339497967343079617494367056318836942927116622 | 92 |
UVM_ERROR @ 102739311 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 102739311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 48223130156054560535224467453038795283874675125916259951068405259689760734569 | 29793 |
UVM_ERROR @ 10125374591 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 10125374591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 37521865993319607117225587887141419558675966077329864023141158079626883602445 | 23535 |
UVM_ERROR @ 8335539288 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 8335539288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 59193800545788422416256896664412814070327985775794204047962694392209532618702 | 5521 |
UVM_ERROR @ 466612465 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 466612465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 61983754677721454259520439239953228017943230805293128338892584694056598859146 | 28260 |
UVM_ERROR @ 31479965518 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 31479965518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 26981574322775431886826148884502826921856912657487299792749703897956967221167 | 7491 |
UVM_ERROR @ 206072387 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 206072387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 31701657961102148434787147715008974903636120952716757291366926870081521053893 | 92 |
UVM_ERROR @ 102732198 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 102732198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 38549713500190334729494387229029239533088109921848014457150604905168337368465 | 141 |
UVM_ERROR @ 55516921 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 55516921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 98483729742462234369483388196074084901523570106324088062525987242598372276905 | 92 |
UVM_ERROR @ 27375495 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 27375495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 38073219411270605495237211862115822261643836495118689774989479055504763942076 | 93 |
UVM_ERROR @ 430985633 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 430985633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 70239679033830710766129411535417950820069130537836844494394229605302721776047 | 142 |
UVM_ERROR @ 5506734537 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 5506734537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 80630048052074200050980762092731716073587743517312211878683247973487806880882 | 92 |
UVM_ERROR @ 26757293 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 26757293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 95237803427850179174617564293102004825084554202649941833862010964011223499625 | 1148 |
UVM_ERROR @ 142241059 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 142241059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 44580651179156722964163269968624624990317697200383373426618138683325699836410 | 11134 |
UVM_ERROR @ 30889533916 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 30889533916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 15526650562523207621766419792209972231024690441396474949942566231301075927303 | 11439 |
UVM_ERROR @ 15158967770 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 15158967770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 47599642026470064821209837310884583677926773655177189453205255151997165484414 | 2850 |
UVM_ERROR @ 227538873 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 227538873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 73357217166294876941486974407002809877887715297193327693913323334847570178487 | 92 |
UVM_ERROR @ 429502138 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 429502138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 24101875387767356165674490561359286353885041216107110107437713790613343138791 | 4251 |
UVM_ERROR @ 59288118543 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 59288118543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 82440515673365905638021770415948355949212886999704837383123254987843818929885 | 49868 |
UVM_ERROR @ 2999042647 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 2999042647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 67410924425204443011067587147678472992506179410812124398826327610049554799379 | 9287 |
UVM_ERROR @ 5703539996 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 5703539996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 26898446516740210116109903919362176244464390721162784543450296868842318273618 | 1436 |
UVM_ERROR @ 9540320881 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 9540320881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 42164476201892225967424333518986991801441552716279558555009889187774809436056 | 15014 |
UVM_ERROR @ 523923717 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 523923717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 69882611709058930503650304875687653924236383833169068365789659131260946181824 | 408 |
UVM_ERROR @ 161243984 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 161243984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 89795534625081810619998608177792992976606755147721365913231477710642338120293 | 11451 |
UVM_ERROR @ 9381005330 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 9381005330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 23916768720523624016287521877100784639196112938898350492952930732242278794985 | 37266 |
UVM_ERROR @ 6655191028 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 6655191028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 19551351032231638017937809725835242050775683975348344570355468228016598148552 | 92 |
UVM_ERROR @ 28047777 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 28047777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 17418169613221434295624900659286901249574996155100966925952751008796958577725 | 1158 |
UVM_ERROR @ 1620286864 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 1620286864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 107636639903747855380291200021595564781519143290974132870453363403549030087191 | 92 |
UVM_ERROR @ 55212733 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 55212733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 76819999194344905307010746034993743468111978292967511228314355521979512553870 | 6818 |
UVM_ERROR @ 284724367 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 284724367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 78790682916306201614251131649438398229319588737678980174368528080554197787529 | 93 |
UVM_ERROR @ 103967553 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 103967553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 44115521678333112741190534685119585283261648325660444241356396401104419524275 | 27660 |
UVM_ERROR @ 7378554289 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 7378554289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 105686555990132107387472435780111647921333027376151426466372161031211189830793 | 92 |
UVM_ERROR @ 60402107 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 60402107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_csr_mem_rw_with_rand_reset | 114370029467494743686932916892973894173965290689213355928606485685372541757537 | 98 |
UVM_ERROR @ 927463389 ps: (otp_ctrl_scoreboard.sv:1825) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
UVM_INFO @ 927463389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert fatal_macro_error did not trigger max_delay:* | ||||
| otp_ctrl_macro_errs | 109926397359164217526258955719897401550210374158857527550785884560336055493549 | 269 |
UVM_ERROR @ 43495011 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_macro_error did not trigger max_delay:20
UVM_INFO @ 43495011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 8876522944218511657847612503338222457899362074573100642549092330462067442665 | 2596 |
UVM_ERROR @ 452226476 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_macro_error did not trigger max_delay:20
UVM_INFO @ 452226476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_macro_errs | 57103479587389792792176721290640108086009760431375857114031464338982701540757 | 6373 |
UVM_ERROR @ 540754140 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_macro_error did not trigger max_delay:20
UVM_INFO @ 540754140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * | ||||
| otp_ctrl_stress_all_with_rand_reset | 65154349188518645427736669036994375893534276885968392629438125115289244687922 | 15909 |
UVM_ERROR @ 638728144 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 638728144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 113503959715373668881047750786837809991869380716869193375827256741674398016754 | 146 |
UVM_ERROR @ 228520474 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 228520474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 93933785103068859262045821323665227227995072409106223231969395169464451513380 | 546 |
UVM_ERROR @ 2391385033 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 2391385033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 8786664634042660426950152852935035860167493106253597931965133648340223511319 | 16235 |
UVM_ERROR @ 7162660692 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 7162660692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 84360944068598970175334722438016718003367914971686048911815566136193525455562 | 92 |
UVM_ERROR @ 54742922 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 54742922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 42691552584833084055394542983791642101684285506751847139727948736335018513077 | 92 |
UVM_ERROR @ 428688982 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 428688982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 111281093157271174137735919073318459438283786663528500377797807125306173844327 | 92 |
UVM_ERROR @ 54406614 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 54406614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 31445696072439903993256173116909123738404253481984104751463431353418253611818 | 92 |
UVM_ERROR @ 26812669 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 26812669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 91018671065585642653457381803354841176533880217670456479484147564226406257700 | 6851 |
UVM_ERROR @ 20291450562 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 20291450562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_csr_mem_rw_with_rand_reset | 43882350713007242158781196123899863271365419910873442988976972532689270818732 | 92 |
UVM_ERROR @ 27897618 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 27897618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_csr_mem_rw_with_rand_reset | 91790228210079611751656763208023905937979188004616766675687276929910839452058 | 92 |
UVM_ERROR @ 26817249 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 26817249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_csr_mem_rw_with_rand_reset | 66671631611385966675860947312797001092517869884985728677217895607049906641376 | 98 |
UVM_ERROR @ 62419275 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 62419275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_csr_mem_rw_with_rand_reset | 7024845070780954746706188268643933485514467910534182146720843474429261795656 | 92 |
UVM_ERROR @ 103579391 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 103579391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:1315) [otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_check_error does not trigger! | ||||
| otp_ctrl_init_fail | 31261662111578917064687928287013344444833568280719885687438501939859971842493 | 3529 |
UVM_ERROR @ 125389308 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 125389308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 62795766186626683746311459107279276957080021441180386254885154041411253731492 | 1469 |
UVM_ERROR @ 468148356 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 468148356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 58299898248069330562978387070621784766577720486354532978960010696271777247575 | 1333 |
UVM_ERROR @ 2178945313 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 2178945313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 12249665415074661732248985099059825169538391247551599940319373845459816742152 | 2345 |
UVM_ERROR @ 336439422 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 336439422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 64648997459520906593175510968081159162946233461869148288398310265736227723291 | 1629 |
UVM_ERROR @ 2081064192 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 2081064192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 27362197656063470963119716107351238517303361121493631294545337448197418777126 | 1921 |
UVM_ERROR @ 484049146 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 484049146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 87122271317473491746563829434224875318954956879526421257193206822915609579254 | 2307 |
UVM_ERROR @ 169250552 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 169250552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 6918441742386708140863982048308301107796184592473749647754785843795687722142 | 2607 |
UVM_ERROR @ 347710535 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 347710535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 45875513684467717875280992802868503913952543631186335605882872012470197447016 | 1567 |
UVM_ERROR @ 1836438149 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 1836438149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 30658189024495745836617162847571404543152941299213513823242811538539171447594 | 3447 |
UVM_ERROR @ 1237215898 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 1237215898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 29302520789180071094169858308364044968619252620891545606158588556780937105113 | 2623 |
UVM_ERROR @ 1013020988 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 1013020988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 36085846947694484760190265226249651702182117535561492233101406106069604988941 | 1569 |
UVM_ERROR @ 410424303 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 410424303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 3382670878033659816389491036105987298623978220675549440738354481602792680666 | 1829 |
UVM_ERROR @ 844367650 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 844367650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 60056040325889409737389829505629743472156827051707085857899896350191519506432 | 1161 |
UVM_ERROR @ 1460957061 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 1460957061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 29681898075717790422139131829279343463549829743032500804220317823443108888951 | 2567 |
UVM_ERROR @ 296528512 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 296528512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 83501680488488674706290785116668919792162111844270930682607851916327134440393 | 1809 |
UVM_ERROR @ 291939016 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 291939016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_init_fail | 67031956239030774808226557293127496773303062049709852500493390206816618152036 | 2301 |
UVM_ERROR @ 959710097 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 959710097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* | ||||
| otp_ctrl_check_fail | 54359111152613177082792789365942701174381989485189322314575115105657874987051 | 2670 |
UVM_ERROR @ 474576042 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.err_code_11
UVM_INFO @ 474576042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (otp_ctrl_scoreboard.sv:958) [scoreboard] Check failed (csr.get_mirrored_value() | status_mask) == (item.d_data | status_mask) (* [*] vs * [*]) reg name: status, compare_mask * | ||||
| otp_ctrl_check_fail | 100817452766843092900702728029291746408754243707130890254428180749253981797918 | 3572 |
UVM_ERROR @ 785825698 ps: (otp_ctrl_scoreboard.sv:958) [uvm_test_top.env.scoreboard] Check failed (csr.get_mirrored_value() | status_mask) == (item.d_data | status_mask) (259 [0x103] vs 257 [0x101]) reg name: status, compare_mask 0
UVM_INFO @ 785825698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (alert_receiver_driver.sv:218) [driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q | ||||
| otp_ctrl_init_fail | 87541663711340329233870175625423896213628844497585636930377413400680244876956 | 1911 |
UVM_FATAL @ 122174750 ps: (alert_receiver_driver.sv:218) [uvm_test_top.env.m_alert_agent_fatal_macro_error.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
UVM_INFO @ 122174750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otp_ctrl_stress_all_with_rand_reset | 40959403679682409277430148160767300590188620412154536412331203112428531921211 | 10801 |
UVM_FATAL @ 470251623 ps: (alert_receiver_driver.sv:218) [uvm_test_top.env.m_alert_agent_fatal_check_error.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
UVM_INFO @ 470251623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * | ||||
| otp_ctrl_stress_all_with_rand_reset | 2065939563158279870866737356073979268193215556600139768457194078149127800957 | 6440 |
UVM_ERROR @ 24611808136 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: 0x0
UVM_INFO @ 24611808136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch | ||||
| otp_ctrl_stress_all_with_rand_reset | 73398849469508738923632741529345877682662794071652174949572752754546832362807 | 14546 |
UVM_ERROR @ 4248820096 ps: (otp_ctrl_base_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 376 [0x178]) dai addr 178 rdata0 readout mismatch
UVM_INFO @ 4248820096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen | ||||
| otp_ctrl_stress_all_with_rand_reset | 56647751253732764122424993669979022395896980894297856924977585505350087210746 | 353 |
UVM_ERROR @ 127617413 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
UVM_INFO @ 127617413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| otp_ctrl_stress_all_with_rand_reset | 107755755557733359960095461532752139020123919719054752670233608489962634451013 | 231 |
UVM_ERROR @ 403071838 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
UVM_INFO @ 403071838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR (otp_ctrl_scoreboard.sv:691) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: OtpErr | ||||
| otp_ctrl_check_fail | 58858679663042013429726574003914634506159957338803569229817830496163805002410 | 2414 |
UVM_ERROR @ 336540635 ps: (otp_ctrl_scoreboard.sv:691) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x0 [0] vs 0x1 [1]) Interrupt_pin: OtpErr
UVM_INFO @ 336540635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| otp_ctrl_check_fail | 43685813322019977278928752824467133915825207835381587307133978650806397230285 | 439 |
UVM_ERROR @ 175747735 ps: (otp_ctrl_scoreboard.sv:691) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x0 [0] vs 0x1 [1]) Interrupt_pin: OtpErr
UVM_INFO @ 175747735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| otp_ctrl_check_fail | 89661961739455645476032351785800173146502500050140333707109505772387606527537 | 7934 |
UVM_ERROR @ 2008197086 ps: (otp_ctrl_scoreboard.sv:691) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x0 [0] vs 0x1 [1]) Interrupt_pin: OtpErr
UVM_INFO @ 2008197086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| otp_ctrl_macro_errs | 17247295216667394768472010471900818575816372459893638482293043822910164935238 | 10578 |
UVM_ERROR @ 1688503765 ps: (otp_ctrl_scoreboard.sv:691) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x0 [0] vs 0x1 [1]) Interrupt_pin: OtpErr
UVM_INFO @ 1688503765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR (cip_base_vseq.sv:1236) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | ||||
| otp_ctrl_stress_all_with_rand_reset | 51927432406961990203899515858179171503821068022935484015243895834332847311760 | 9083 |
UVM_ERROR @ 32791367005 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 32791367005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR (otp_ctrl_scoreboard.sv:277) [scoreboard] Check failed exp_alert != OtpNoAlert (* [*] vs * [*]) | ||||
| otp_ctrl_stress_all_with_rand_reset | 63413434734586590666506558944439435163476478637329499190409577089787647334838 | 1018 |
UVM_ERROR @ 73302427 ps: (otp_ctrl_scoreboard.sv:277) [uvm_test_top.env.scoreboard] Check failed exp_alert != OtpNoAlert (0 [0x0] vs 0 [0x0])
UVM_INFO @ 73302427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| otp_ctrl_stress_all_with_rand_reset | 39424022305602923143349262520084394340327426820114656401225104919888187861580 | 26313 |
UVM_ERROR @ 5747034832 ps: (otp_ctrl_scoreboard.sv:277) [uvm_test_top.env.scoreboard] Check failed exp_alert != OtpNoAlert (0 [0x0] vs 0 [0x0])
UVM_INFO @ 5747034832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| Offending '(cio_test_en_o == *)' | ||||
| otp_ctrl_stress_all_with_rand_reset | 44217108750178947445879693000660032609047872312450540125145087144743231929312 | 11947 |
Offending '(cio_test_en_o == 0)'
UVM_ERROR @ 3329095039 ps: (otp_ctrl_if.sv:297) [ASSERT FAILED] CioTestEnOWithDftOff_A
UVM_INFO @ 3329095039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| otp_ctrl_csr_mem_rw_with_rand_reset | 48067352957667430952257893166363325242762521039986497689373449867896388612356 | 93 |
Offending '(cio_test_en_o == 0)'
UVM_ERROR @ 27048286 ps: (otp_ctrl_if.sv:297) [ASSERT FAILED] CioTestEnOWithDftOff_A
UVM_INFO @ 27048286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR (cip_base_vseq.sv:1315) [otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_macro_error does not trigger! | ||||
| otp_ctrl_init_fail | 9844238525510356090448470144817579427549745682545229136791531562340401694229 | 1125 |
UVM_ERROR @ 1445969046 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_macro_error does not trigger!
UVM_INFO @ 1445969046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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