Simulation Results: rom_ctrl/32kb

 
02/05/2026 09:12:14 DVSim: v1.17.3 sha: 63c8a50 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.51 %
  • code
  • 99.68 %
  • assert
  • 96.80 %
  • func
  • 99.05 %
  • line
  • 99.59 %
  • branch
  • 100.00 %
  • cond
  • 98.81 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
97.10%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 7.780s 343.688us 2 2 100.00
csr_hw_reset 5 5 100.00
rom_ctrl_csr_hw_reset 9.530s 578.470us 5 5 100.00
csr_rw 20 20 100.00
rom_ctrl_csr_rw 7.080s 180.426us 20 20 100.00
csr_bit_bash 5 5 100.00
rom_ctrl_csr_bit_bash 7.390s 3114.023us 5 5 100.00
csr_aliasing 5 5 100.00
rom_ctrl_csr_aliasing 5.760s 169.961us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 7.030s 325.504us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rom_ctrl_csr_rw 7.080s 180.426us 20 20 100.00
rom_ctrl_csr_aliasing 5.760s 169.961us 5 5 100.00
mem_walk 5 5 100.00
rom_ctrl_mem_walk 5.130s 518.457us 5 5 100.00
mem_partial_access 5 5 100.00
rom_ctrl_mem_partial_access 5.650s 515.083us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 6.450s 308.277us 2 2 100.00
stress_all 20 20 100.00
rom_ctrl_stress_all 25.050s 3020.054us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 11.080s 397.733us 2 2 100.00
alert_test 50 50 100.00
rom_ctrl_alert_test 7.240s 550.008us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rom_ctrl_tl_errors 11.400s 612.107us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rom_ctrl_tl_errors 11.400s 612.107us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rom_ctrl_csr_hw_reset 9.530s 578.470us 5 5 100.00
rom_ctrl_csr_rw 7.080s 180.426us 20 20 100.00
rom_ctrl_csr_aliasing 5.760s 169.961us 5 5 100.00
rom_ctrl_same_csr_outstanding 9.070s 562.273us 20 20 100.00
tl_d_partial_access 50 50 100.00
rom_ctrl_csr_hw_reset 9.530s 578.470us 5 5 100.00
rom_ctrl_csr_rw 7.080s 180.426us 20 20 100.00
rom_ctrl_csr_aliasing 5.760s 169.961us 5 5 100.00
rom_ctrl_same_csr_outstanding 9.070s 562.273us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 118.680s 1944.615us 18 20 90.00
passthru_mem_tl_intg_err 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 32.860s 662.249us 20 20 100.00
tl_intg_err 25 25 100.00
rom_ctrl_sec_cm 298.010s 615.008us 5 5 100.00
rom_ctrl_tl_intg_err 65.650s 794.382us 20 20 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 298.010s 615.008us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 298.010s 615.008us 5 5 100.00
sec_cm_checker_ctr_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 118.680s 1944.615us 18 20 90.00
sec_cm_checker_ctrl_flow_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 118.680s 1944.615us 18 20 90.00
sec_cm_checker_fsm_local_esc 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 118.680s 1944.615us 18 20 90.00
sec_cm_compare_ctrl_flow_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 118.680s 1944.615us 18 20 90.00
sec_cm_compare_ctr_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 118.680s 1944.615us 18 20 90.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 298.010s 615.008us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 298.010s 615.008us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 7.780s 343.688us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 7.780s 343.688us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 7.780s 343.688us 2 2 100.00
sec_cm_bus_integrity 20 20 100.00
rom_ctrl_tl_intg_err 65.650s 794.382us 20 20 100.00
sec_cm_bus_local_esc 20 22 90.91
rom_ctrl_corrupt_sig_fatal_chk 118.680s 1944.615us 18 20 90.00
rom_ctrl_kmac_err_chk 11.080s 397.733us 2 2 100.00
sec_cm_mux_mubi 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 118.680s 1944.615us 18 20 90.00
sec_cm_mux_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 118.680s 1944.615us 18 20 90.00
sec_cm_ctrl_redun 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 118.680s 1944.615us 18 20 90.00
sec_cm_ctrl_mem_integrity 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 32.860s 662.249us 20 20 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 298.010s 615.008us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 20 20 100.00
rom_ctrl_stress_all_with_rand_reset 289.590s 3922.877us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
rom_ctrl_corrupt_sig_fatal_chk 32746573118044015627188905030843530926650381899937191425032479068683188733879 84
UVM_ERROR @ 296674923 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 296674923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 25875773820505256985348250309407406123400299841812068624215787298187639586855 109
UVM_ERROR @ 2954679840 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 2954679840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---