Simulation Results: rstmgr

 
02/05/2026 09:12:14 DVSim: v1.17.3 sha: 63c8a50 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.86 %
  • code
  • 99.68 %
  • assert
  • 98.13 %
  • func
  • 98.76 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 99.38 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
rstmgr_smoke 1.580s 242.202us 50 50 100.00
csr_hw_reset 5 5 100.00
rstmgr_csr_hw_reset 0.930s 136.152us 5 5 100.00
csr_rw 20 20 100.00
rstmgr_csr_rw 0.810s 67.358us 20 20 100.00
csr_bit_bash 5 5 100.00
rstmgr_csr_bit_bash 3.490s 800.629us 5 5 100.00
csr_aliasing 5 5 100.00
rstmgr_csr_aliasing 1.560s 149.618us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.320s 182.655us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rstmgr_csr_rw 0.810s 67.358us 20 20 100.00
rstmgr_csr_aliasing 1.560s 149.618us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 50 50 100.00
rstmgr_por_stretcher 1.210s 220.574us 50 50 100.00
sw_rst 50 50 100.00
rstmgr_sw_rst 2.180s 539.945us 50 50 100.00
sw_rst_reset_race 50 50 100.00
rstmgr_sw_rst_reset_race 1.610s 288.117us 50 50 100.00
reset_info 50 50 100.00
rstmgr_reset 6.630s 2130.924us 50 50 100.00
cpu_info 50 50 100.00
rstmgr_reset 6.630s 2130.924us 50 50 100.00
alert_info 50 50 100.00
rstmgr_reset 6.630s 2130.924us 50 50 100.00
reset_info_capture 50 50 100.00
rstmgr_reset 6.630s 2130.924us 50 50 100.00
stress_all 50 50 100.00
rstmgr_stress_all 42.620s 16532.240us 50 50 100.00
alert_test 50 50 100.00
rstmgr_alert_test 0.940s 184.569us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rstmgr_tl_errors 3.040s 580.569us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rstmgr_tl_errors 3.040s 580.569us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rstmgr_csr_hw_reset 0.930s 136.152us 5 5 100.00
rstmgr_csr_rw 0.810s 67.358us 20 20 100.00
rstmgr_csr_aliasing 1.560s 149.618us 5 5 100.00
rstmgr_same_csr_outstanding 1.310s 197.662us 20 20 100.00
tl_d_partial_access 50 50 100.00
rstmgr_csr_hw_reset 0.930s 136.152us 5 5 100.00
rstmgr_csr_rw 0.810s 67.358us 20 20 100.00
rstmgr_csr_aliasing 1.560s 149.618us 5 5 100.00
rstmgr_same_csr_outstanding 1.310s 197.662us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
rstmgr_sec_cm 21.020s 16828.545us 5 5 100.00
rstmgr_tl_intg_err 2.820s 932.338us 20 20 100.00
prim_count_check 5 5 100.00
rstmgr_sec_cm 21.020s 16828.545us 5 5 100.00
prim_fsm_check 5 5 100.00
rstmgr_sec_cm 21.020s 16828.545us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
rstmgr_tl_intg_err 2.820s 932.338us 20 20 100.00
sec_cm_scan_intersig_mubi 50 50 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.220s 148.151us 50 50 100.00
sec_cm_leaf_rst_bkgn_chk 50 50 100.00
rstmgr_leaf_rst_cnsty 6.240s 2448.139us 50 50 100.00
sec_cm_leaf_rst_shadow 50 50 100.00
rstmgr_leaf_rst_shadow_attack 1.280s 301.487us 50 50 100.00
sec_cm_leaf_fsm_sparse 5 5 100.00
rstmgr_sec_cm 21.020s 16828.545us 5 5 100.00
sec_cm_sw_rst_config_regwen 20 20 100.00
rstmgr_csr_rw 0.810s 67.358us 20 20 100.00
sec_cm_dump_ctrl_config_regwen 20 20 100.00
rstmgr_csr_rw 0.810s 67.358us 20 20 100.00