Simulation Results: rstmgr_cnsty_chk

 
02/05/2026 09:12:14 DVSim: v1.17.3 sha: 63c8a50 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.52 %
  • code
  • 95.05 %
  • assert
  • 100.00 %
  • line
  • 98.41 %
  • branch
  • 98.31 %
  • cond
  • 86.21 %
  • toggle
  • 100.00 %
  • FSM
  • 92.31 %
Validation stages
unmapped
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 9 10 90.00
rstmgr_cnsty_chk_test 3.210s 10769.763us 9 10 90.00

Error Messages

   Test seed line log context
UVM_ERROR (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) || (delta_cycles > -1) || (error_count == *))
rstmgr_cnsty_chk_test 96978290042883569189435867403942539964125271466467956320387811452204735904368 175
UVM_ERROR @ 1798226239 ps: (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) || (delta_cycles > -1) || (error_count == 0))
UVM_INFO @ 1816306239 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -11 total errors 0 / 16
UVM_INFO @ 1834386239 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -10 total errors 0 / 16
UVM_INFO @ 1852466239 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -9 total errors 0 / 16
UVM_INFO @ 1870546239 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -8 total errors 0 / 16