Simulation Results: spi_device/2p

 
02/05/2026 09:12:14 DVSim: v1.17.3 sha: 63c8a50 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.09 %
  • code
  • 94.28 %
  • assert
  • 94.74 %
  • func
  • 99.26 %
  • line
  • 99.16 %
  • branch
  • 98.49 %
  • cond
  • 96.65 %
  • toggle
  • 87.74 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
spi_device_flash_and_tpm 419.660s 125325.182us 50 50 100.00
csr_hw_reset 5 5 100.00
spi_device_csr_hw_reset 1.220s 82.297us 5 5 100.00
csr_rw 20 20 100.00
spi_device_csr_rw 2.380s 110.102us 20 20 100.00
csr_bit_bash 5 5 100.00
spi_device_csr_bit_bash 24.310s 2437.480us 5 5 100.00
csr_aliasing 5 5 100.00
spi_device_csr_aliasing 16.140s 1112.905us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
spi_device_csr_mem_rw_with_rand_reset 3.160s 482.206us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
spi_device_csr_rw 2.380s 110.102us 20 20 100.00
spi_device_csr_aliasing 16.140s 1112.905us 5 5 100.00
mem_walk 5 5 100.00
spi_device_mem_walk 0.740s 39.832us 5 5 100.00
mem_partial_access 5 5 100.00
spi_device_mem_partial_access 1.890s 253.272us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 50 50 100.00
spi_device_csb_read 1.230s 25.580us 50 50 100.00
mem_parity 20 20 100.00
spi_device_mem_parity 1.470s 33.938us 20 20 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 1.100s 23.609us 1 1 100.00
tpm_read 50 50 100.00
spi_device_tpm_rw 4.320s 1409.068us 50 50 100.00
tpm_write 50 50 100.00
spi_device_tpm_rw 4.320s 1409.068us 50 50 100.00
tpm_hw_reg 100 100 100.00
spi_device_tpm_read_hw_reg 25.310s 25467.409us 50 50 100.00
spi_device_tpm_sts_read 1.330s 712.901us 50 50 100.00
tpm_fully_random_case 50 50 100.00
spi_device_tpm_all 53.820s 8649.266us 50 50 100.00
pass_cmd_filtering 100 100 100.00
spi_device_pass_cmd_filtering 31.900s 34560.962us 50 50 100.00
spi_device_flash_all 391.550s 312976.747us 50 50 100.00
pass_addr_translation 100 100 100.00
spi_device_pass_addr_payload_swap 36.670s 34588.393us 50 50 100.00
spi_device_flash_all 391.550s 312976.747us 50 50 100.00
pass_payload_translation 100 100 100.00
spi_device_pass_addr_payload_swap 36.670s 34588.393us 50 50 100.00
spi_device_flash_all 391.550s 312976.747us 50 50 100.00
cmd_info_slots 50 50 100.00
spi_device_flash_all 391.550s 312976.747us 50 50 100.00
cmd_read_status 100 100 100.00
spi_device_intercept 38.240s 14862.029us 50 50 100.00
spi_device_flash_all 391.550s 312976.747us 50 50 100.00
cmd_read_jedec 100 100 100.00
spi_device_intercept 38.240s 14862.029us 50 50 100.00
spi_device_flash_all 391.550s 312976.747us 50 50 100.00
cmd_read_sfdp 100 100 100.00
spi_device_intercept 38.240s 14862.029us 50 50 100.00
spi_device_flash_all 391.550s 312976.747us 50 50 100.00
cmd_fast_read 100 100 100.00
spi_device_intercept 38.240s 14862.029us 50 50 100.00
spi_device_flash_all 391.550s 312976.747us 50 50 100.00
cmd_read_pipeline 100 100 100.00
spi_device_intercept 38.240s 14862.029us 50 50 100.00
spi_device_flash_all 391.550s 312976.747us 50 50 100.00
flash_cmd_upload 50 50 100.00
spi_device_upload 29.320s 71217.617us 50 50 100.00
mailbox_command 50 50 100.00
spi_device_mailbox 77.560s 175473.367us 50 50 100.00
mailbox_cross_outside_command 50 50 100.00
spi_device_mailbox 77.560s 175473.367us 50 50 100.00
mailbox_cross_inside_command 50 50 100.00
spi_device_mailbox 77.560s 175473.367us 50 50 100.00
cmd_read_buffer 100 100 100.00
spi_device_flash_mode 55.330s 16305.549us 50 50 100.00
spi_device_read_buffer_direct 19.780s 7577.881us 50 50 100.00
cmd_dummy_cycle 100 100 100.00
spi_device_mailbox 77.560s 175473.367us 50 50 100.00
spi_device_flash_all 391.550s 312976.747us 50 50 100.00
quad_spi 50 50 100.00
spi_device_flash_all 391.550s 312976.747us 50 50 100.00
dual_spi 50 50 100.00
spi_device_flash_all 391.550s 312976.747us 50 50 100.00
4b_3b_feature 50 50 100.00
spi_device_cfg_cmd 18.670s 9563.998us 50 50 100.00
write_enable_disable 50 50 100.00
spi_device_cfg_cmd 18.670s 9563.998us 50 50 100.00
TPM_with_flash_or_passthrough_mode 50 50 100.00
spi_device_flash_and_tpm 419.660s 125325.182us 50 50 100.00
tpm_and_flash_trans_with_min_inactive_time 50 50 100.00
spi_device_flash_and_tpm_min_idle 457.520s 236674.101us 50 50 100.00
stress_all 50 50 100.00
spi_device_stress_all 688.860s 543382.676us 50 50 100.00
alert_test 50 50 100.00
spi_device_alert_test 1.130s 15.165us 50 50 100.00
intr_test 50 50 100.00
spi_device_intr_test 1.030s 12.826us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
spi_device_tl_errors 4.460s 239.340us 20 20 100.00
tl_d_illegal_access 20 20 100.00
spi_device_tl_errors 4.460s 239.340us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
spi_device_csr_hw_reset 1.220s 82.297us 5 5 100.00
spi_device_csr_rw 2.380s 110.102us 20 20 100.00
spi_device_csr_aliasing 16.140s 1112.905us 5 5 100.00
spi_device_same_csr_outstanding 3.490s 585.311us 20 20 100.00
tl_d_partial_access 50 50 100.00
spi_device_csr_hw_reset 1.220s 82.297us 5 5 100.00
spi_device_csr_rw 2.380s 110.102us 20 20 100.00
spi_device_csr_aliasing 16.140s 1112.905us 5 5 100.00
spi_device_same_csr_outstanding 3.490s 585.311us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
spi_device_tl_intg_err 18.730s 9671.459us 20 20 100.00
spi_device_sec_cm 1.560s 244.719us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
spi_device_tl_intg_err 18.730s 9671.459us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 50 50 100.00
spi_device_flash_mode_ignore_cmds 332.600s 55464.457us 50 50 100.00