Simulation Results: spi_host

 
02/05/2026 09:12:14 DVSim: v1.17.3 sha: 63c8a50 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.83 %
  • code
  • 95.08 %
  • assert
  • 95.64 %
  • func
  • 90.76 %
  • block
  • 97.05 %
  • line
  • 98.76 %
  • branch
  • 93.55 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.61%
V2S
100.00%
unmapped
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
spi_host_smoke 138.000s 11674.673us 50 50 100.00
csr_hw_reset 5 5 100.00
spi_host_csr_hw_reset 2.000s 16.432us 5 5 100.00
csr_rw 20 20 100.00
spi_host_csr_rw 2.000s 16.942us 20 20 100.00
csr_bit_bash 5 5 100.00
spi_host_csr_bit_bash 4.000s 3033.457us 5 5 100.00
csr_aliasing 5 5 100.00
spi_host_csr_aliasing 2.000s 20.051us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 24.211us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
spi_host_csr_rw 2.000s 16.942us 20 20 100.00
spi_host_csr_aliasing 2.000s 20.051us 5 5 100.00
mem_walk 5 5 100.00
spi_host_mem_walk 1.000s 17.455us 5 5 100.00
mem_partial_access 5 5 100.00
spi_host_mem_partial_access 2.000s 22.061us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 50 50 100.00
spi_host_performance 34.000s 70.595us 50 50 100.00
error_event_intr 150 150 100.00
spi_host_overflow_underflow 36.000s 463.408us 50 50 100.00
spi_host_error_cmd 34.000s 23.030us 50 50 100.00
spi_host_event 465.000s 45863.360us 50 50 100.00
clock_rate 49 50 98.00
spi_host_speed 46.000s 200000.000us 49 50 98.00
speed 49 50 98.00
spi_host_speed 46.000s 200000.000us 49 50 98.00
chip_select_timing 49 50 98.00
spi_host_speed 46.000s 200000.000us 49 50 98.00
sw_reset 50 50 100.00
spi_host_sw_reset 80.000s 4468.639us 50 50 100.00
passthrough_mode 50 50 100.00
spi_host_passthrough_mode 34.000s 23.204us 50 50 100.00
cpol_cpha 49 50 98.00
spi_host_speed 46.000s 200000.000us 49 50 98.00
full_cycle 49 50 98.00
spi_host_speed 46.000s 200000.000us 49 50 98.00
duplex 50 50 100.00
spi_host_smoke 138.000s 11674.673us 50 50 100.00
tx_rx_only 50 50 100.00
spi_host_smoke 138.000s 11674.673us 50 50 100.00
stress_all 48 50 96.00
spi_host_stress_all 1358.000s 1000000.000us 48 50 96.00
spien 50 50 100.00
spi_host_spien 102.000s 19919.502us 50 50 100.00
stall 50 50 100.00
spi_host_status_stall 363.000s 352288.333us 50 50 100.00
Idlecsbactive 50 50 100.00
spi_host_idlecsbactive 44.000s 2352.972us 50 50 100.00
data_fifo_status 50 50 100.00
spi_host_overflow_underflow 36.000s 463.408us 50 50 100.00
alert_test 50 50 100.00
spi_host_alert_test 34.000s 18.413us 50 50 100.00
intr_test 50 50 100.00
spi_host_intr_test 2.000s 19.363us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
spi_host_tl_errors 3.000s 70.571us 20 20 100.00
tl_d_illegal_access 20 20 100.00
spi_host_tl_errors 3.000s 70.571us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
spi_host_csr_hw_reset 2.000s 16.432us 5 5 100.00
spi_host_csr_rw 2.000s 16.942us 20 20 100.00
spi_host_csr_aliasing 2.000s 20.051us 5 5 100.00
spi_host_same_csr_outstanding 2.000s 25.812us 20 20 100.00
tl_d_partial_access 50 50 100.00
spi_host_csr_hw_reset 2.000s 16.432us 5 5 100.00
spi_host_csr_rw 2.000s 16.942us 20 20 100.00
spi_host_csr_aliasing 2.000s 20.051us 5 5 100.00
spi_host_same_csr_outstanding 2.000s 25.812us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
spi_host_sec_cm 34.000s 165.116us 5 5 100.00
spi_host_tl_intg_err 2.000s 93.812us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
spi_host_tl_intg_err 2.000s 93.812us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 8 10 80.00
spi_host_upper_range_clkdiv 699.000s 100051.875us 8 10 80.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
spi_host_upper_range_clkdiv 22267512533539039995357658879536248329418557700919674005538871927879304779153 115
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
spi_host_stress_all 27826146382573299697503815585301862518944013823942492472236898292166588490311 333
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
spi_host_speed 45825575135734746576685522725833562749261804859384520190307594156918986917141 151
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=*
spi_host_upper_range_clkdiv 83604935877494229844879236827644345172061305217302800687892383664108632034405 149
UVM_FATAL @ 100051875171 ps: (spi_host_base_vseq.sv:237) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 100000000ns spi_host_reg_block.status.active (addr=0x14943f94, Comparison=CompareOpEq, exp_data=0x0, call_count=15
UVM_INFO @ 100051875171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [spi_host_smoke_vseq] wait timeout occurred!
spi_host_stress_all 36143869391439561623464474002709313871903474105088889984254541618909898183993 83
UVM_FATAL @ 10008049945 ps: (cip_base_vseq.sv:454) [uvm_test_top.env.virtual_sequencer.spi_host_smoke_vseq] wait timeout occurred!
UVM_INFO @ 10008049945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---