Simulation Results: sram_ctrl/main

 
02/05/2026 09:12:14 DVSim: v1.17.3 sha: 63c8a50 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.67 %
  • code
  • 96.96 %
  • assert
  • 96.46 %
  • func
  • 96.60 %
  • block
  • 96.35 %
  • line
  • 97.11 %
  • branch
  • 94.65 %
  • toggle
  • 96.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 5 5 100.00
sram_ctrl_smoke 7.000s 702.284us 5 5 100.00
csr_hw_reset 5 5 100.00
sram_ctrl_csr_hw_reset 2.000s 93.527us 5 5 100.00
csr_rw 20 20 100.00
sram_ctrl_csr_rw 2.000s 52.319us 20 20 100.00
csr_bit_bash 5 5 100.00
sram_ctrl_csr_bit_bash 3.000s 172.845us 5 5 100.00
csr_aliasing 5 5 100.00
sram_ctrl_csr_aliasing 2.000s 43.142us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 4.000s 1435.725us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sram_ctrl_csr_rw 2.000s 52.319us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 43.142us 5 5 100.00
mem_walk 5 5 100.00
sram_ctrl_mem_walk 281.000s 53250.403us 5 5 100.00
mem_partial_access 5 5 100.00
sram_ctrl_mem_partial_access 159.000s 9983.108us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 5 5 100.00
sram_ctrl_multiple_keys 49.000s 29644.721us 5 5 100.00
stress_pipeline 5 5 100.00
sram_ctrl_stress_pipeline 277.000s 25476.165us 5 5 100.00
bijection 5 5 100.00
sram_ctrl_bijection 187.000s 6159.614us 5 5 100.00
access_during_key_req 5 5 100.00
sram_ctrl_access_during_key_req 117.000s 13584.293us 5 5 100.00
lc_escalation 5 5 100.00
sram_ctrl_lc_escalation 56.000s 12852.629us 5 5 100.00
executable 5 5 100.00
sram_ctrl_executable 74.000s 6868.373us 5 5 100.00
partial_access 10 10 100.00
sram_ctrl_partial_access 6.000s 3097.373us 5 5 100.00
sram_ctrl_partial_access_b2b 312.000s 41293.544us 5 5 100.00
max_throughput 15 15 100.00
sram_ctrl_max_throughput 7.000s 1276.319us 5 5 100.00
sram_ctrl_throughput_w_partial_write 7.000s 688.509us 5 5 100.00
sram_ctrl_throughput_w_readback 7.000s 3198.888us 5 5 100.00
regwen 5 5 100.00
sram_ctrl_regwen 16.000s 16456.170us 5 5 100.00
ram_cfg 5 5 100.00
sram_ctrl_ram_cfg 5.000s 710.728us 5 5 100.00
stress_all 5 5 100.00
sram_ctrl_stress_all 753.000s 264578.146us 5 5 100.00
alert_test 50 50 100.00
sram_ctrl_alert_test 2.000s 32.069us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sram_ctrl_tl_errors 5.000s 630.965us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sram_ctrl_tl_errors 5.000s 630.965us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sram_ctrl_csr_hw_reset 2.000s 93.527us 5 5 100.00
sram_ctrl_csr_rw 2.000s 52.319us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 43.142us 5 5 100.00
sram_ctrl_same_csr_outstanding 2.000s 47.175us 20 20 100.00
tl_d_partial_access 50 50 100.00
sram_ctrl_csr_hw_reset 2.000s 93.527us 5 5 100.00
sram_ctrl_csr_rw 2.000s 52.319us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 43.142us 5 5 100.00
sram_ctrl_same_csr_outstanding 2.000s 47.175us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 45.000s 14604.250us 20 20 100.00
tl_intg_err 25 25 100.00
sram_ctrl_tl_intg_err 5.000s 1208.488us 20 20 100.00
sram_ctrl_sec_cm 6.000s 1801.084us 5 5 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 6.000s 1801.084us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
sram_ctrl_tl_intg_err 5.000s 1208.488us 20 20 100.00
sec_cm_ctrl_config_regwen 5 5 100.00
sram_ctrl_regwen 16.000s 16456.170us 5 5 100.00
sec_cm_readback_config_regwen 5 5 100.00
sram_ctrl_regwen 16.000s 16456.170us 5 5 100.00
sec_cm_exec_config_regwen 20 20 100.00
sram_ctrl_csr_rw 2.000s 52.319us 20 20 100.00
sec_cm_exec_config_mubi 5 5 100.00
sram_ctrl_executable 74.000s 6868.373us 5 5 100.00
sec_cm_exec_intersig_mubi 5 5 100.00
sram_ctrl_executable 74.000s 6868.373us 5 5 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 5 5 100.00
sram_ctrl_executable 74.000s 6868.373us 5 5 100.00
sec_cm_lc_escalate_en_intersig_mubi 5 5 100.00
sram_ctrl_lc_escalation 56.000s 12852.629us 5 5 100.00
sec_cm_prim_ram_ctrl_mubi 5 5 100.00
sram_ctrl_mubi_enc_err 9.000s 8450.766us 5 5 100.00
sec_cm_mem_integrity 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 45.000s 14604.250us 20 20 100.00
sec_cm_mem_readback 5 5 100.00
sram_ctrl_readback_err 11.000s 11077.039us 5 5 100.00
sec_cm_mem_scramble 5 5 100.00
sram_ctrl_smoke 7.000s 702.284us 5 5 100.00
sec_cm_addr_scramble 5 5 100.00
sram_ctrl_smoke 7.000s 702.284us 5 5 100.00
sec_cm_instr_bus_lc_gated 5 5 100.00
sram_ctrl_executable 74.000s 6868.373us 5 5 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 6.000s 1801.084us 5 5 100.00
sec_cm_key_global_esc 5 5 100.00
sram_ctrl_lc_escalation 56.000s 12852.629us 5 5 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 6.000s 1801.084us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 6.000s 1801.084us 5 5 100.00
sec_cm_scramble_key_sideload 5 5 100.00
sram_ctrl_smoke 7.000s 702.284us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 6.000s 1801.084us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 5 100.00
sram_ctrl_stress_all_with_rand_reset 53.000s 4712.951us 5 5 100.00