| V1 |
|
97.14% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 5 | 5 | 100.00 | |||
| sram_ctrl_smoke | 2.000s | 163.926us | 5 | 5 | 100.00 | |
| csr_hw_reset | 5 | 5 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 1.000s | 26.485us | 5 | 5 | 100.00 | |
| csr_rw | 20 | 20 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 14.440us | 20 | 20 | 100.00 | |
| csr_bit_bash | 5 | 5 | 100.00 | |||
| sram_ctrl_csr_bit_bash | 3.000s | 127.994us | 5 | 5 | 100.00 | |
| csr_aliasing | 5 | 5 | 100.00 | |||
| sram_ctrl_csr_aliasing | 2.000s | 26.053us | 5 | 5 | 100.00 | |
| csr_mem_rw_with_rand_reset | 18 | 20 | 90.00 | |||
| sram_ctrl_csr_mem_rw_with_rand_reset | 3.000s | 127.017us | 18 | 20 | 90.00 | |
| regwen_csr_and_corresponding_lockable_csr | 25 | 25 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 14.440us | 20 | 20 | 100.00 | |
| sram_ctrl_csr_aliasing | 2.000s | 26.053us | 5 | 5 | 100.00 | |
| mem_walk | 5 | 5 | 100.00 | |||
| sram_ctrl_mem_walk | 7.000s | 335.960us | 5 | 5 | 100.00 | |
| mem_partial_access | 5 | 5 | 100.00 | |||
| sram_ctrl_mem_partial_access | 5.000s | 497.111us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| multiple_keys | 5 | 5 | 100.00 | |||
| sram_ctrl_multiple_keys | 10.000s | 1955.056us | 5 | 5 | 100.00 | |
| stress_pipeline | 5 | 5 | 100.00 | |||
| sram_ctrl_stress_pipeline | 299.000s | 17095.422us | 5 | 5 | 100.00 | |
| bijection | 5 | 5 | 100.00 | |||
| sram_ctrl_bijection | 6.000s | 330.202us | 5 | 5 | 100.00 | |
| access_during_key_req | 5 | 5 | 100.00 | |||
| sram_ctrl_access_during_key_req | 23.000s | 806.773us | 5 | 5 | 100.00 | |
| lc_escalation | 5 | 5 | 100.00 | |||
| sram_ctrl_lc_escalation | 7.000s | 1339.743us | 5 | 5 | 100.00 | |
| executable | 5 | 5 | 100.00 | |||
| sram_ctrl_executable | 8.000s | 7843.065us | 5 | 5 | 100.00 | |
| partial_access | 10 | 10 | 100.00 | |||
| sram_ctrl_partial_access | 2.000s | 176.773us | 5 | 5 | 100.00 | |
| sram_ctrl_partial_access_b2b | 227.000s | 20450.774us | 5 | 5 | 100.00 | |
| max_throughput | 15 | 15 | 100.00 | |||
| sram_ctrl_max_throughput | 2.000s | 35.569us | 5 | 5 | 100.00 | |
| sram_ctrl_throughput_w_partial_write | 3.000s | 37.907us | 5 | 5 | 100.00 | |
| sram_ctrl_throughput_w_readback | 3.000s | 72.312us | 5 | 5 | 100.00 | |
| regwen | 5 | 5 | 100.00 | |||
| sram_ctrl_regwen | 13.000s | 751.153us | 5 | 5 | 100.00 | |
| ram_cfg | 5 | 5 | 100.00 | |||
| sram_ctrl_ram_cfg | 2.000s | 49.878us | 5 | 5 | 100.00 | |
| stress_all | 5 | 5 | 100.00 | |||
| sram_ctrl_stress_all | 38.000s | 17867.164us | 5 | 5 | 100.00 | |
| alert_test | 50 | 50 | 100.00 | |||
| sram_ctrl_alert_test | 2.000s | 14.381us | 50 | 50 | 100.00 | |
| tl_d_oob_addr_access | 20 | 20 | 100.00 | |||
| sram_ctrl_tl_errors | 5.000s | 576.018us | 20 | 20 | 100.00 | |
| tl_d_illegal_access | 20 | 20 | 100.00 | |||
| sram_ctrl_tl_errors | 5.000s | 576.018us | 20 | 20 | 100.00 | |
| tl_d_outstanding_access | 50 | 50 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 1.000s | 26.485us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_rw | 2.000s | 14.440us | 20 | 20 | 100.00 | |
| sram_ctrl_csr_aliasing | 2.000s | 26.053us | 5 | 5 | 100.00 | |
| sram_ctrl_same_csr_outstanding | 2.000s | 97.668us | 20 | 20 | 100.00 | |
| tl_d_partial_access | 50 | 50 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 1.000s | 26.485us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_rw | 2.000s | 14.440us | 20 | 20 | 100.00 | |
| sram_ctrl_csr_aliasing | 2.000s | 26.053us | 5 | 5 | 100.00 | |
| sram_ctrl_same_csr_outstanding | 2.000s | 97.668us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| passthru_mem_tl_intg_err | 20 | 20 | 100.00 | |||
| sram_ctrl_passthru_mem_tl_intg_err | 5.000s | 444.178us | 20 | 20 | 100.00 | |
| tl_intg_err | 25 | 25 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 1419.716us | 5 | 5 | 100.00 | |
| sram_ctrl_tl_intg_err | 3.000s | 1079.679us | 20 | 20 | 100.00 | |
| prim_count_check | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 1419.716us | 5 | 5 | 100.00 | |
| sec_cm_bus_integrity | 20 | 20 | 100.00 | |||
| sram_ctrl_tl_intg_err | 3.000s | 1079.679us | 20 | 20 | 100.00 | |
| sec_cm_ctrl_config_regwen | 5 | 5 | 100.00 | |||
| sram_ctrl_regwen | 13.000s | 751.153us | 5 | 5 | 100.00 | |
| sec_cm_readback_config_regwen | 5 | 5 | 100.00 | |||
| sram_ctrl_regwen | 13.000s | 751.153us | 5 | 5 | 100.00 | |
| sec_cm_exec_config_regwen | 20 | 20 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 14.440us | 20 | 20 | 100.00 | |
| sec_cm_exec_config_mubi | 5 | 5 | 100.00 | |||
| sram_ctrl_executable | 8.000s | 7843.065us | 5 | 5 | 100.00 | |
| sec_cm_exec_intersig_mubi | 5 | 5 | 100.00 | |||
| sram_ctrl_executable | 8.000s | 7843.065us | 5 | 5 | 100.00 | |
| sec_cm_lc_hw_debug_en_intersig_mubi | 5 | 5 | 100.00 | |||
| sram_ctrl_executable | 8.000s | 7843.065us | 5 | 5 | 100.00 | |
| sec_cm_lc_escalate_en_intersig_mubi | 5 | 5 | 100.00 | |||
| sram_ctrl_lc_escalation | 7.000s | 1339.743us | 5 | 5 | 100.00 | |
| sec_cm_prim_ram_ctrl_mubi | 5 | 5 | 100.00 | |||
| sram_ctrl_mubi_enc_err | 2.000s | 131.212us | 5 | 5 | 100.00 | |
| sec_cm_mem_integrity | 20 | 20 | 100.00 | |||
| sram_ctrl_passthru_mem_tl_intg_err | 5.000s | 444.178us | 20 | 20 | 100.00 | |
| sec_cm_mem_readback | 5 | 5 | 100.00 | |||
| sram_ctrl_readback_err | 2.000s | 74.251us | 5 | 5 | 100.00 | |
| sec_cm_mem_scramble | 5 | 5 | 100.00 | |||
| sram_ctrl_smoke | 2.000s | 163.926us | 5 | 5 | 100.00 | |
| sec_cm_addr_scramble | 5 | 5 | 100.00 | |||
| sram_ctrl_smoke | 2.000s | 163.926us | 5 | 5 | 100.00 | |
| sec_cm_instr_bus_lc_gated | 5 | 5 | 100.00 | |||
| sram_ctrl_executable | 8.000s | 7843.065us | 5 | 5 | 100.00 | |
| sec_cm_ram_tl_lc_gate_fsm_sparse | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 1419.716us | 5 | 5 | 100.00 | |
| sec_cm_key_global_esc | 5 | 5 | 100.00 | |||
| sram_ctrl_lc_escalation | 7.000s | 1339.743us | 5 | 5 | 100.00 | |
| sec_cm_key_local_esc | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 1419.716us | 5 | 5 | 100.00 | |
| sec_cm_init_ctr_redun | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 1419.716us | 5 | 5 | 100.00 | |
| sec_cm_scramble_key_sideload | 5 | 5 | 100.00 | |||
| sram_ctrl_smoke | 2.000s | 163.926us | 5 | 5 | 100.00 | |
| sec_cm_tlul_fifo_ctr_redun | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 1419.716us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 5 | 5 | 100.00 | |||
| sram_ctrl_stress_all_with_rand_reset | 58.000s | 3746.496us | 5 | 5 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * | ||||
| sram_ctrl_csr_mem_rw_with_rand_reset | 9944425068533785334159749779471511686111813497730051171504805244294455404504 | 88 |
UVM_ERROR @ 109262213 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (12 [0xc] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
UVM_INFO @ 109262213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| sram_ctrl_csr_mem_rw_with_rand_reset | 100180641133812318185508957546840779146839138856375342293171334910656842807570 | 88 |
UVM_ERROR @ 27125410 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (14 [0xe] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
UVM_INFO @ 27125410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|