Simulation Results: aes/masked

 
09/05/2026 22:36:56 DVSim: v1.34.0 sha: f3ee88d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.64 %
  • code
  • 96.67 %
  • assert
  • 98.38 %
  • func
  • 97.87 %
  • block
  • 97.07 %
  • line
  • 98.20 %
  • branch
  • 92.73 %
  • toggle
  • 97.99 %
  • FSM
  • 97.78 %
Validation stages
V1
100.00%
V2
100.00%
V2S
97.57%
V3
40.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 65.505us 1 1 100.00
smoke 50 50 100.00
aes_smoke 20.000s 798.169us 50 50 100.00
csr_hw_reset 5 5 100.00
aes_csr_hw_reset 33.000s 61.176us 5 5 100.00
csr_rw 20 20 100.00
aes_csr_rw 30.000s 71.376us 20 20 100.00
csr_bit_bash 5 5 100.00
aes_csr_bit_bash 35.000s 188.562us 5 5 100.00
csr_aliasing 5 5 100.00
aes_csr_aliasing 34.000s 187.251us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
aes_csr_mem_rw_with_rand_reset 31.000s 253.594us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
aes_csr_rw 30.000s 71.376us 20 20 100.00
aes_csr_aliasing 34.000s 187.251us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 150 150 100.00
aes_smoke 20.000s 798.169us 50 50 100.00
aes_config_error 61.000s 1114.902us 50 50 100.00
aes_stress 67.000s 3963.543us 50 50 100.00
key_length 150 150 100.00
aes_smoke 20.000s 798.169us 50 50 100.00
aes_config_error 61.000s 1114.902us 50 50 100.00
aes_stress 67.000s 3963.543us 50 50 100.00
back2back 100 100 100.00
aes_stress 67.000s 3963.543us 50 50 100.00
aes_b2b 42.000s 188.058us 50 50 100.00
backpressure 50 50 100.00
aes_stress 67.000s 3963.543us 50 50 100.00
multi_message 200 200 100.00
aes_smoke 20.000s 798.169us 50 50 100.00
aes_config_error 61.000s 1114.902us 50 50 100.00
aes_stress 67.000s 3963.543us 50 50 100.00
aes_alert_reset 35.000s 139.255us 50 50 100.00
failure_test 150 150 100.00
aes_man_cfg_err 31.000s 57.734us 50 50 100.00
aes_config_error 61.000s 1114.902us 50 50 100.00
aes_alert_reset 35.000s 139.255us 50 50 100.00
trigger_clear_test 50 50 100.00
aes_clear 36.000s 626.930us 50 50 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 34.000s 3994.289us 1 1 100.00
reset_recovery 50 50 100.00
aes_alert_reset 35.000s 139.255us 50 50 100.00
stress 50 50 100.00
aes_stress 67.000s 3963.543us 50 50 100.00
sideload 100 100 100.00
aes_stress 67.000s 3963.543us 50 50 100.00
aes_sideload 13.000s 221.209us 50 50 100.00
deinitialization 50 50 100.00
aes_deinit 32.000s 216.436us 50 50 100.00
stress_all 10 10 100.00
aes_stress_all 107.000s 3912.223us 10 10 100.00
alert_test 50 50 100.00
aes_alert_test 33.000s 64.666us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
aes_tl_errors 4.000s 268.406us 20 20 100.00
tl_d_illegal_access 20 20 100.00
aes_tl_errors 4.000s 268.406us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
aes_csr_hw_reset 33.000s 61.176us 5 5 100.00
aes_csr_rw 30.000s 71.376us 20 20 100.00
aes_csr_aliasing 34.000s 187.251us 5 5 100.00
aes_same_csr_outstanding 18.000s 207.252us 20 20 100.00
tl_d_partial_access 50 50 100.00
aes_csr_hw_reset 33.000s 61.176us 5 5 100.00
aes_csr_rw 30.000s 71.376us 20 20 100.00
aes_csr_aliasing 34.000s 187.251us 5 5 100.00
aes_same_csr_outstanding 18.000s 207.252us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 50 50 100.00
aes_reseed 24.000s 131.992us 50 50 100.00
fault_inject 674 700 96.29
aes_fi 32.000s 354.107us 50 50 100.00
aes_control_fi 61.000s 0.000us 280 300 93.33
aes_cipher_fi 32.000s 64.955us 344 350 98.29
shadow_reg_update_error 19 20 95.00
aes_shadow_reg_errors 11.000s 84.493us 19 20 95.00
shadow_reg_read_clear_staged_value 19 20 95.00
aes_shadow_reg_errors 11.000s 84.493us 19 20 95.00
shadow_reg_storage_error 19 20 95.00
aes_shadow_reg_errors 11.000s 84.493us 19 20 95.00
shadowed_reset_glitch 19 20 95.00
aes_shadow_reg_errors 11.000s 84.493us 19 20 95.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
aes_shadow_reg_errors_with_csr_rw 12.000s 455.457us 20 20 100.00
tl_intg_err 24 25 96.00
aes_sec_cm 21.000s 3342.962us 5 5 100.00
aes_tl_intg_err 4.000s 867.229us 19 20 95.00
sec_cm_bus_integrity 19 20 95.00
aes_tl_intg_err 4.000s 867.229us 19 20 95.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
aes_alert_reset 35.000s 139.255us 50 50 100.00
sec_cm_main_config_shadow 19 20 95.00
aes_shadow_reg_errors 11.000s 84.493us 19 20 95.00
sec_cm_gcm_config_shadow 19 20 95.00
aes_shadow_reg_errors 11.000s 84.493us 19 20 95.00
sec_cm_main_config_sparse 218 220 99.09
aes_smoke 20.000s 798.169us 50 50 100.00
aes_stress 67.000s 3963.543us 50 50 100.00
aes_alert_reset 35.000s 139.255us 50 50 100.00
aes_core_fi 57.000s 10029.783us 68 70 97.14
sec_cm_gcm_config_sparse 168 170 98.82
aes_config_error 61.000s 1114.902us 50 50 100.00
aes_stress 67.000s 3963.543us 50 50 100.00
aes_core_fi 57.000s 10029.783us 68 70 97.14
sec_cm_aux_config_shadow 19 20 95.00
aes_shadow_reg_errors 11.000s 84.493us 19 20 95.00
sec_cm_aux_config_regwen 100 100 100.00
aes_readability 27.000s 92.844us 50 50 100.00
aes_stress 67.000s 3963.543us 50 50 100.00
sec_cm_key_sideload 100 100 100.00
aes_stress 67.000s 3963.543us 50 50 100.00
aes_sideload 13.000s 221.209us 50 50 100.00
sec_cm_key_sw_unreadable 50 50 100.00
aes_readability 27.000s 92.844us 50 50 100.00
sec_cm_data_reg_sw_unreadable 50 50 100.00
aes_readability 27.000s 92.844us 50 50 100.00
sec_cm_key_sec_wipe 50 50 100.00
aes_readability 27.000s 92.844us 50 50 100.00
sec_cm_iv_config_sec_wipe 50 50 100.00
aes_readability 27.000s 92.844us 50 50 100.00
sec_cm_data_reg_sec_wipe 50 50 100.00
aes_readability 27.000s 92.844us 50 50 100.00
sec_cm_data_reg_key_sca 50 50 100.00
aes_stress 67.000s 3963.543us 50 50 100.00
sec_cm_key_masking 50 50 100.00
aes_stress 67.000s 3963.543us 50 50 100.00
sec_cm_main_fsm_sparse 50 50 100.00
aes_fi 32.000s 354.107us 50 50 100.00
sec_cm_main_fsm_redun 724 750 96.53
aes_fi 32.000s 354.107us 50 50 100.00
aes_control_fi 61.000s 0.000us 280 300 93.33
aes_cipher_fi 32.000s 64.955us 344 350 98.29
aes_ctr_fi 32.000s 197.108us 50 50 100.00
sec_cm_cipher_fsm_sparse 50 50 100.00
aes_fi 32.000s 354.107us 50 50 100.00
sec_cm_cipher_fsm_redun 674 700 96.29
aes_fi 32.000s 354.107us 50 50 100.00
aes_control_fi 61.000s 0.000us 280 300 93.33
aes_cipher_fi 32.000s 64.955us 344 350 98.29
sec_cm_cipher_ctr_redun 344 350 98.29
aes_cipher_fi 32.000s 64.955us 344 350 98.29
sec_cm_ctr_fsm_sparse 50 50 100.00
aes_fi 32.000s 354.107us 50 50 100.00
sec_cm_ctr_fsm_redun 380 400 95.00
aes_fi 32.000s 354.107us 50 50 100.00
aes_control_fi 61.000s 0.000us 280 300 93.33
aes_ctr_fi 32.000s 197.108us 50 50 100.00
sec_cm_ghash_fsm_sparse 50 50 100.00
aes_fi 32.000s 354.107us 50 50 100.00
sec_cm_ctrl_sparse 724 750 96.53
aes_fi 32.000s 354.107us 50 50 100.00
aes_control_fi 61.000s 0.000us 280 300 93.33
aes_cipher_fi 32.000s 64.955us 344 350 98.29
aes_ctr_fi 32.000s 197.108us 50 50 100.00
sec_cm_main_fsm_global_esc 50 50 100.00
aes_alert_reset 35.000s 139.255us 50 50 100.00
sec_cm_main_fsm_local_esc 724 750 96.53
aes_fi 32.000s 354.107us 50 50 100.00
aes_control_fi 61.000s 0.000us 280 300 93.33
aes_cipher_fi 32.000s 64.955us 344 350 98.29
aes_ctr_fi 32.000s 197.108us 50 50 100.00
sec_cm_cipher_fsm_local_esc 724 750 96.53
aes_fi 32.000s 354.107us 50 50 100.00
aes_control_fi 61.000s 0.000us 280 300 93.33
aes_cipher_fi 32.000s 64.955us 344 350 98.29
aes_ctr_fi 32.000s 197.108us 50 50 100.00
sec_cm_ctr_fsm_local_esc 380 400 95.00
aes_fi 32.000s 354.107us 50 50 100.00
aes_control_fi 61.000s 0.000us 280 300 93.33
aes_ctr_fi 32.000s 197.108us 50 50 100.00
sec_cm_ghash_fsm_local_esc 50 50 100.00
aes_fi 32.000s 354.107us 50 50 100.00
sec_cm_data_reg_local_esc 674 700 96.29
aes_fi 32.000s 354.107us 50 50 100.00
aes_control_fi 61.000s 0.000us 280 300 93.33
aes_cipher_fi 32.000s 64.955us 344 350 98.29
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 4 10 40.00
aes_stress_all_with_rand_reset 179.000s 3822.944us 4 10 40.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! 12 test runs
aes_control_fi 32218466321178175306080829919398401726594650032887097462382357041216846606849 143
UVM_INFO @ 10016306183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 101141328049121914234243934943947075420699436953894951296331346276246110440887 145
UVM_INFO @ 10007224343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 84120690344482429335162442576352718404783543763707599898453153707876247445189 148
UVM_INFO @ 10008230080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 54847988506687216148878951406724372195718091519075822831520831764250528527635 145
UVM_INFO @ 10007801366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 72879497964840485220683527612396076110401211230455614347138533942995073173013 145
UVM_INFO @ 10013646008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 57532947234568062415730181675328972675247080227747099735098035184512478672796 145
UVM_INFO @ 10013807419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 88178922053175994687191773457156468457930616263347800921881324487925793537505 151
UVM_INFO @ 10009746529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 956249907360182186792060573185008507616046951711292295814309771083821834956 151
UVM_INFO @ 10003440829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 57018828920121813807728919731202159851510293927479775067385326603934419562136 146
UVM_INFO @ 10038931185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 10602770211427254882478659263545779844486352436173631731112489720475261948206 148
UVM_INFO @ 10031728737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 36668392066824722852145513543861691910926501366380881084836952684957645894455 146
UVM_INFO @ 10009223920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 43988340829865043443623359344602024115749802913339162284185785177397704738283 154
UVM_INFO @ 10024075688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 8 test runs
aes_control_fi 42832511316877221590956001103264575876953162312802223478443490280492382409542 None
aes_control_fi 52398494021199467422672961053211650322822419381991358922695854565435645624420 None
aes_control_fi 114268372808317000331976936836578540311596661711752466742122506659256505563104 None
aes_control_fi 100161617289305449777625859494162210978146349352845341944111197268854547454824 None
aes_control_fi 62738146991436760127846949853211727230671497019659894784644946724741868949803 None
aes_control_fi 88154771194139100660148568736208899094843617811377522074394222326170540415591 None
aes_control_fi 97048119838214292180231911127003227407585565387672126062834842244086212775496 None
aes_control_fi 52351801072729818212397669746747682144690838277119598177068491879319683630914 None
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! 6 test runs
aes_cipher_fi 50908599641316755121931129228970916166388195918774564336758109131093864712472 152
UVM_INFO @ 10147561400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 70095359782957134692251360645986506532611814964926887203825652303495728125178 153
UVM_INFO @ 10005253780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 12571869098960606289273989825852859650516737917779742354067369645574351146456 142
UVM_INFO @ 10035258313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 25896024422477303268020500463447897907933747835398763772267232083133723623076 144
UVM_INFO @ 10026151681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 26040493407587813987363840233481355830292267606254663186197112523554937450877 143
UVM_INFO @ 10009141211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 43827707607954946994396062508060913074250086303433338168325873310582497070128 149
UVM_INFO @ 10020645989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:76) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 2 test runs
aes_stress_all_with_rand_reset 75384138108464472638418501478827082596134989171127424879399193162599748163819 1121
UVM_INFO @ 1127673878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 82515540606007529023316654117746650366175279178382948888409398787424112422734 1266
UVM_INFO @ 4868559029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:76) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 2 test runs
aes_stress_all_with_rand_reset 55373673973281939840505213074735694844845901984065566350516580276864375786705 326
UVM_INFO @ 449300022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 10955053124708131996212752028057100369330730075173157382263305215496168562957 1279
UVM_INFO @ 3158199976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 2 test runs
aes_stress_all_with_rand_reset 104698728351669748620983676647418625096966515369672605385658284936858952658420 922
UVM_INFO @ 3177443674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 80354550852988484500940992268863622667735665160250724381099063180279065799536 1584
UVM_INFO @ 6244144661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_core_fi_vseq.sv:70) [aes_core_fi_vseq] wait timeout occurred! 2 test runs
aes_core_fi 55409697037003123006097412071681846310260455588041723961318076234720885545289 140
UVM_INFO @ 10029782594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 100109423194252249069438644770081626952026377995741047316659902044274004879540 140
UVM_INFO @ 10005671164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1028) virtual_sequencer [aes_common_vseq] expect alert:fatal_fault to fire 1 test run
aes_tl_intg_err 51700758230430988900778082537075729937358557449881265981145576776387993328958 113
UVM_INFO @ 25182127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: aes_reg_block_extended.ctrl_shadowed reset value: * 1 test run
aes_shadow_reg_errors 108686299260812852490637791782748957515040185724540319923007012300789333196375 106
UVM_INFO @ 4452357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---