Simulation Results: aes/unmasked

 
09/05/2026 22:36:56 DVSim: v1.34.0 sha: f3ee88d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.20 %
  • code
  • 93.38 %
  • assert
  • 98.11 %
  • func
  • 97.10 %
  • block
  • 94.27 %
  • line
  • 96.02 %
  • branch
  • 87.58 %
  • toggle
  • 98.08 %
  • FSM
  • 91.85 %
Validation stages
V1
100.00%
V2
99.83%
V2S
95.95%
V3
20.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 160.573us 1 1 100.00
smoke 50 50 100.00
aes_smoke 7.000s 374.721us 50 50 100.00
csr_hw_reset 5 5 100.00
aes_csr_hw_reset 2.000s 62.444us 5 5 100.00
csr_rw 20 20 100.00
aes_csr_rw 3.000s 123.521us 20 20 100.00
csr_bit_bash 5 5 100.00
aes_csr_bit_bash 9.000s 3050.801us 5 5 100.00
csr_aliasing 5 5 100.00
aes_csr_aliasing 3.000s 88.705us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
aes_csr_mem_rw_with_rand_reset 3.000s 72.199us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
aes_csr_rw 3.000s 123.521us 20 20 100.00
aes_csr_aliasing 3.000s 88.705us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 150 150 100.00
aes_smoke 7.000s 374.721us 50 50 100.00
aes_config_error 6.000s 835.930us 50 50 100.00
aes_stress 4.000s 132.280us 50 50 100.00
key_length 150 150 100.00
aes_smoke 7.000s 374.721us 50 50 100.00
aes_config_error 6.000s 835.930us 50 50 100.00
aes_stress 4.000s 132.280us 50 50 100.00
back2back 100 100 100.00
aes_stress 4.000s 132.280us 50 50 100.00
aes_b2b 7.000s 165.995us 50 50 100.00
backpressure 50 50 100.00
aes_stress 4.000s 132.280us 50 50 100.00
multi_message 200 200 100.00
aes_smoke 7.000s 374.721us 50 50 100.00
aes_config_error 6.000s 835.930us 50 50 100.00
aes_stress 4.000s 132.280us 50 50 100.00
aes_alert_reset 3.000s 458.281us 50 50 100.00
failure_test 150 150 100.00
aes_man_cfg_err 3.000s 116.925us 50 50 100.00
aes_config_error 6.000s 835.930us 50 50 100.00
aes_alert_reset 3.000s 458.281us 50 50 100.00
trigger_clear_test 49 50 98.00
aes_clear 3.000s 160.200us 49 50 98.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 444.928us 1 1 100.00
reset_recovery 50 50 100.00
aes_alert_reset 3.000s 458.281us 50 50 100.00
stress 50 50 100.00
aes_stress 4.000s 132.280us 50 50 100.00
sideload 100 100 100.00
aes_stress 4.000s 132.280us 50 50 100.00
aes_sideload 4.000s 263.494us 50 50 100.00
deinitialization 50 50 100.00
aes_deinit 3.000s 282.972us 50 50 100.00
stress_all 10 10 100.00
aes_stress_all 22.000s 15473.821us 10 10 100.00
alert_test 50 50 100.00
aes_alert_test 3.000s 55.086us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
aes_tl_errors 3.000s 195.292us 20 20 100.00
tl_d_illegal_access 20 20 100.00
aes_tl_errors 3.000s 195.292us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
aes_csr_hw_reset 2.000s 62.444us 5 5 100.00
aes_csr_rw 3.000s 123.521us 20 20 100.00
aes_csr_aliasing 3.000s 88.705us 5 5 100.00
aes_same_csr_outstanding 3.000s 791.294us 20 20 100.00
tl_d_partial_access 50 50 100.00
aes_csr_hw_reset 2.000s 62.444us 5 5 100.00
aes_csr_rw 3.000s 123.521us 20 20 100.00
aes_csr_aliasing 3.000s 88.705us 5 5 100.00
aes_same_csr_outstanding 3.000s 791.294us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 50 50 100.00
aes_reseed 4.000s 574.129us 50 50 100.00
fault_inject 654 700 93.43
aes_fi 4.000s 502.757us 49 50 98.00
aes_control_fi 61.000s 0.000us 279 300 93.00
aes_cipher_fi 62.045s 0.000us 326 350 93.14
shadow_reg_update_error 19 20 95.00
aes_shadow_reg_errors 8.000s 10085.174us 19 20 95.00
shadow_reg_read_clear_staged_value 19 20 95.00
aes_shadow_reg_errors 8.000s 10085.174us 19 20 95.00
shadow_reg_storage_error 19 20 95.00
aes_shadow_reg_errors 8.000s 10085.174us 19 20 95.00
shadowed_reset_glitch 19 20 95.00
aes_shadow_reg_errors 8.000s 10085.174us 19 20 95.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
aes_shadow_reg_errors_with_csr_rw 4.000s 445.006us 20 20 100.00
tl_intg_err 25 25 100.00
aes_sec_cm 5.000s 762.938us 5 5 100.00
aes_tl_intg_err 4.000s 295.207us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
aes_tl_intg_err 4.000s 295.207us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
aes_alert_reset 3.000s 458.281us 50 50 100.00
sec_cm_main_config_shadow 19 20 95.00
aes_shadow_reg_errors 8.000s 10085.174us 19 20 95.00
sec_cm_gcm_config_shadow 19 20 95.00
aes_shadow_reg_errors 8.000s 10085.174us 19 20 95.00
sec_cm_main_config_sparse 218 220 99.09
aes_smoke 7.000s 374.721us 50 50 100.00
aes_stress 4.000s 132.280us 50 50 100.00
aes_alert_reset 3.000s 458.281us 50 50 100.00
aes_core_fi 178.000s 10018.846us 68 70 97.14
sec_cm_gcm_config_sparse 168 170 98.82
aes_config_error 6.000s 835.930us 50 50 100.00
aes_stress 4.000s 132.280us 50 50 100.00
aes_core_fi 178.000s 10018.846us 68 70 97.14
sec_cm_aux_config_shadow 19 20 95.00
aes_shadow_reg_errors 8.000s 10085.174us 19 20 95.00
sec_cm_aux_config_regwen 100 100 100.00
aes_readability 3.000s 67.021us 50 50 100.00
aes_stress 4.000s 132.280us 50 50 100.00
sec_cm_key_sideload 100 100 100.00
aes_stress 4.000s 132.280us 50 50 100.00
aes_sideload 4.000s 263.494us 50 50 100.00
sec_cm_key_sw_unreadable 50 50 100.00
aes_readability 3.000s 67.021us 50 50 100.00
sec_cm_data_reg_sw_unreadable 50 50 100.00
aes_readability 3.000s 67.021us 50 50 100.00
sec_cm_key_sec_wipe 50 50 100.00
aes_readability 3.000s 67.021us 50 50 100.00
sec_cm_iv_config_sec_wipe 50 50 100.00
aes_readability 3.000s 67.021us 50 50 100.00
sec_cm_data_reg_sec_wipe 50 50 100.00
aes_readability 3.000s 67.021us 50 50 100.00
sec_cm_data_reg_key_sca 50 50 100.00
aes_stress 4.000s 132.280us 50 50 100.00
sec_cm_key_masking 50 50 100.00
aes_stress 4.000s 132.280us 50 50 100.00
sec_cm_main_fsm_sparse 49 50 98.00
aes_fi 4.000s 502.757us 49 50 98.00
sec_cm_main_fsm_redun 703 750 93.73
aes_fi 4.000s 502.757us 49 50 98.00
aes_control_fi 61.000s 0.000us 279 300 93.00
aes_cipher_fi 62.045s 0.000us 326 350 93.14
aes_ctr_fi 60.000s 0.000us 49 50 98.00
sec_cm_cipher_fsm_sparse 49 50 98.00
aes_fi 4.000s 502.757us 49 50 98.00
sec_cm_cipher_fsm_redun 654 700 93.43
aes_fi 4.000s 502.757us 49 50 98.00
aes_control_fi 61.000s 0.000us 279 300 93.00
aes_cipher_fi 62.045s 0.000us 326 350 93.14
sec_cm_cipher_ctr_redun 326 350 93.14
aes_cipher_fi 62.045s 0.000us 326 350 93.14
sec_cm_ctr_fsm_sparse 49 50 98.00
aes_fi 4.000s 502.757us 49 50 98.00
sec_cm_ctr_fsm_redun 377 400 94.25
aes_fi 4.000s 502.757us 49 50 98.00
aes_control_fi 61.000s 0.000us 279 300 93.00
aes_ctr_fi 60.000s 0.000us 49 50 98.00
sec_cm_ghash_fsm_sparse 49 50 98.00
aes_fi 4.000s 502.757us 49 50 98.00
sec_cm_ctrl_sparse 703 750 93.73
aes_fi 4.000s 502.757us 49 50 98.00
aes_control_fi 61.000s 0.000us 279 300 93.00
aes_cipher_fi 62.045s 0.000us 326 350 93.14
aes_ctr_fi 60.000s 0.000us 49 50 98.00
sec_cm_main_fsm_global_esc 50 50 100.00
aes_alert_reset 3.000s 458.281us 50 50 100.00
sec_cm_main_fsm_local_esc 703 750 93.73
aes_fi 4.000s 502.757us 49 50 98.00
aes_control_fi 61.000s 0.000us 279 300 93.00
aes_cipher_fi 62.045s 0.000us 326 350 93.14
aes_ctr_fi 60.000s 0.000us 49 50 98.00
sec_cm_cipher_fsm_local_esc 703 750 93.73
aes_fi 4.000s 502.757us 49 50 98.00
aes_control_fi 61.000s 0.000us 279 300 93.00
aes_cipher_fi 62.045s 0.000us 326 350 93.14
aes_ctr_fi 60.000s 0.000us 49 50 98.00
sec_cm_ctr_fsm_local_esc 377 400 94.25
aes_fi 4.000s 502.757us 49 50 98.00
aes_control_fi 61.000s 0.000us 279 300 93.00
aes_ctr_fi 60.000s 0.000us 49 50 98.00
sec_cm_ghash_fsm_local_esc 49 50 98.00
aes_fi 4.000s 502.757us 49 50 98.00
sec_cm_data_reg_local_esc 654 700 93.43
aes_fi 4.000s 502.757us 49 50 98.00
aes_control_fi 61.000s 0.000us 279 300 93.00
aes_cipher_fi 62.045s 0.000us 326 350 93.14
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 2 10 20.00
aes_stress_all_with_rand_reset 62.000s 3436.057us 2 10 20.00

Error Messages

   Test seed line log context
Job timed out after * minutes 23 test runs
aes_ctr_fi 10125802566453450827244500596700450897914683718132991339935080387162496640062 None
aes_cipher_fi 27842150327772633878554819183481279155976625050976934217457468467415212267353 None
aes_cipher_fi 70800337124350487475661707361785253162344330855143848958579505807032642018804 None
aes_cipher_fi 82153481757470417201401404806387921666829679723138758660106289855158044779608 None
aes_control_fi 13120871099685378053515857177468203579022696063935956961270736109037470105572 None
aes_control_fi 11924822768984898581901801405422797549723502172180301591852488093667864412799 None
aes_cipher_fi 27350556406116606286721134202782835174732965467187055297681480099392546834991 None
aes_control_fi 30911837557394181920652554865370310096268333961092270531190182801064417614970 None
aes_control_fi 113207926235799179697318098456869016957280624620251586121832513235074165448799 None
aes_control_fi 66590265367505408580402558869916511382455189551062526986243183578636870665689 None
aes_cipher_fi 82149555251346112532947370652257807240932529351102277198621784810589215342930 None
aes_cipher_fi 8705289958759963494095935287788201190837418614154173123498740543125363293576 None
aes_control_fi 98589265988721386621044893155574871688428528075482203370892528179457316704638 None
aes_cipher_fi 31763447890258562663503209354600039277024899853936833671117837288606314832848 None
aes_control_fi 27074418942104204619318300085321532274377541870538711559046425433679907329298 None
aes_cipher_fi 85795155999041631672810153868109824852094095562648049827349758550078661078159 None
aes_cipher_fi 81467357360581469846523787417151836370428725007330963756927860792103673299263 None
aes_cipher_fi 14723255209886138479488601600542408829966037795202798971306076546670981362740 None
aes_cipher_fi 66963106068652684621230521315459462115550504847719019233059346020888519938614 None
aes_control_fi 73602443018871555411325460283503802888704676502552656262852301776748887911398 None
aes_cipher_fi 23366163249991079561356806108849075072774401757506284032737510439702229493994 None
aes_cipher_fi 26054872754316670063378945737175486600244469002069973858540557747900673120977 None
aes_cipher_fi 104303195335873512643740048888303714680772583450851697496270332247709417074957 None
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! 12 test runs
aes_control_fi 93679685304504671171434429771177410887588385709879090796834052578636107475519 146
UVM_INFO @ 10010499180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 39074954707082790922693314762212807349117344665172100197015186774100923121060 148
UVM_INFO @ 10011343749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 45594145554600723538784094850297648980615717811646704294549612170349827821831 144
UVM_INFO @ 10004008981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 64510274274977851674742255091077297674024150664746640296095835596308012888471 141
UVM_INFO @ 10013908330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 67356705174349442917804936239455188894775505559125545011098012883635227780211 145
UVM_INFO @ 10029303047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 61268988930379786324832897027389634717787196418982360160618640243608201108600 148
UVM_INFO @ 10007914847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 45813781495734060130068804936034145100192047423543631246492971620791017660850 148
UVM_INFO @ 10007280137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 76977241746511302400577506098896978357212078735589368000876914360730422168586 140
UVM_INFO @ 10013817971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 14242741051545311430679046933764363457471186609138296597545153213921113339538 150
UVM_INFO @ 10033721212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 95972552506249229717938475758405102959384896142723345851172133930122574658547 152
UVM_INFO @ 10008979634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 112958775427201867813353292449663909855510287436389761570178073871327700199145 149
UVM_INFO @ 10003957508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 35354990555473851201754034943176975780379609545619800385705281522333816310403 153
UVM_INFO @ 10016837679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! 8 test runs
aes_cipher_fi 23678274020592016186432654526006397214840205686684230380139308574428528997669 149
UVM_INFO @ 10010313087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 52733250317813051981577258744009554323571245792047048449308593088878050703875 149
UVM_INFO @ 10028924320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 51305127997419824100574407726016118830125905564267198497508021581257038944963 145
UVM_INFO @ 10010895052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 58940580901389964849655990289108435965883691761753917412618259071500838755429 149
UVM_INFO @ 10061218273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 18172057140077011919683425535996732653636705180505385759751802043043553736280 142
UVM_INFO @ 10005486243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 55519433285942086760271166754580777500875632088117984291728354627588225789481 149
UVM_INFO @ 10029737953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 67390850461543300685110092412212427127340749485043316793098207314500728799537 149
UVM_INFO @ 10006472364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 39280885171429774658092335048763485477972986139105609206983568517182962150238 140
UVM_INFO @ 10007398722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 4 test runs
aes_stress_all_with_rand_reset 33848509490515818999685729615029891759395632019176567359941510587200220736775 1263
UVM_INFO @ 392458665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 58516074960405624983911830193818710158070171844917435739443638670486620359319 935
UVM_INFO @ 2659145202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 47527335337504009609391523476426171413838061242432683605246380445712975785070 476
UVM_INFO @ 558350293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 108859457902576834193345066256719096450483077826285677812676396245697762457595 2278
UVM_INFO @ 1457093716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:76) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 2 test runs
aes_stress_all_with_rand_reset 100064091783576489730405381890218727018197250409661961904959750368642972973342 428
UVM_INFO @ 211866691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 8771966677198484404743026833816559291951739543648341283837674551678054107743 824
UVM_INFO @ 2199954245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 2 test runs
aes_control_fi 33146050738674351003374767370725881573451609764418530126344059208945384997670 148
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 35103852663191450541207319918612933519438430660107903794741463821941214208568 153
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,1142): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) 1 test run
aes_stress_all_with_rand_reset 79305687779941293666102666293900877981949726050309601086992665828421001282034 555
UVM_ERROR @ 496464366 ps: (aes_core.sv:1142) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
UVM_INFO @ 496464366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq__shadow_reg_errors.svh:336) [aes_common_vseq] ctrl_shadowed update_err alert timeout 1 test run
aes_shadow_reg_errors 48329371782097904230567501706300134396942684054070151964488692230277961002279 107
UVM_INFO @ 10085173876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:76) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 1 test run
aes_stress_all_with_rand_reset 97564574783763235552179479647376460255749984396871717108931447486662783215210 300
UVM_INFO @ 687607174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_core_fi_vseq.sv:93) [aes_core_fi_vseq] wait timeout occurred! 1 test run
aes_core_fi 109751292111254791832434772172788658181707372989489652455094567666663487997496 145
UVM_INFO @ 10028515978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,1136): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) 1 test run
aes_fi 112264745146977025566478194723025516799620200518263943958683123632991482221204 984
UVM_ERROR @ 6204704 ps: (aes_core.sv:1136) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
UVM_INFO @ 6204704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:785) scoreboard [scoreboard] # * 1 test run
aes_clear 66205356058412290408237689574690120382940902452650355774875364314417591784618 2911
TEST FAILED MESSAGES DID NOT MATCH
0 9e 96 9d 0
1 00 67 8d 0
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block_extended.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) 1 test run
aes_core_fi 74403782863952730542090491309808432731221317838608882585594088445757638713477 145
UVM_INFO @ 10018845826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_cipher_fi 43455769256832133000449256293081106906139859277698984750037421422688037526492 153
UVM_INFO @ 123105583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---