Simulation Results: chip

 
09/05/2026 22:36:56 DVSim: v1.34.0 sha: f3ee88d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.49 %
  • code
  • 86.09 %
  • assert
  • 98.00 %
  • func
  • 99.39 %
  • line
  • 94.70 %
  • branch
  • 94.40 %
  • cond
  • 92.45 %
  • toggle
  • 91.75 %
  • FSM
  • 57.14 %
Validation stages
V1
94.55%
V2
90.81%
V2S
83.33%
V3
87.42%
unmapped
75.00%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 12 12 100.00
chip_sw_example_flash 256.140s 3305.784us 3 3 100.00
chip_sw_example_rom 107.700s 2485.805us 3 3 100.00
chip_sw_example_manufacturer 197.440s 2749.212us 3 3 100.00
chip_sw_example_concurrency 227.500s 3153.132us 3 3 100.00
csr_hw_reset 5 5 100.00
chip_csr_hw_reset 386.060s 7445.677us 5 5 100.00
csr_rw 20 20 100.00
chip_csr_rw 626.360s 6247.315us 20 20 100.00
csr_bit_bash 5 5 100.00
chip_csr_bit_bash 1014.730s 8963.662us 5 5 100.00
csr_aliasing 5 5 100.00
chip_csr_aliasing 7158.340s 39409.152us 5 5 100.00
csr_mem_rw_with_rand_reset 8 20 40.00
chip_csr_mem_rw_with_rand_reset 805.900s 9501.644us 8 20 40.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
chip_csr_aliasing 7158.340s 39409.152us 5 5 100.00
chip_csr_rw 626.360s 6247.315us 20 20 100.00
xbar_smoke 100 100 100.00
xbar_smoke 11.520s 212.953us 100 100 100.00
chip_sw_gpio_out 3 3 100.00
chip_sw_gpio 418.270s 4124.112us 3 3 100.00
chip_sw_gpio_in 3 3 100.00
chip_sw_gpio 418.270s 4124.112us 3 3 100.00
chip_sw_gpio_irq 3 3 100.00
chip_sw_gpio 418.270s 4124.112us 3 3 100.00
chip_sw_uart_tx_rx 5 5 100.00
chip_sw_uart_tx_rx 506.000s 4808.973us 5 5 100.00
chip_sw_uart_rx_overflow 20 20 100.00
chip_sw_uart_tx_rx 506.000s 4808.973us 5 5 100.00
chip_sw_uart_tx_rx_idx1 517.780s 4309.210us 5 5 100.00
chip_sw_uart_tx_rx_idx2 477.400s 4392.093us 5 5 100.00
chip_sw_uart_tx_rx_idx3 481.460s 4935.637us 5 5 100.00
chip_sw_uart_baud_rate 20 20 100.00
chip_sw_uart_rand_baudrate 2514.740s 12903.740us 20 20 100.00
chip_sw_uart_tx_rx_alt_clk_freq 10 10 100.00
chip_sw_uart_tx_rx_alt_clk_freq 1588.160s 8264.882us 5 5 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 1408.080s 13034.428us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 10 10 100.00
chip_padctrl_attributes 277.720s 5896.768us 10 10 100.00
chip_padctrl_attributes 10 10 100.00
chip_padctrl_attributes 277.720s 5896.768us 10 10 100.00
chip_sw_sleep_pin_mio_dio_val 3 3 100.00
chip_sw_sleep_pin_mio_dio_val 263.840s 3028.783us 3 3 100.00
chip_sw_sleep_pin_wake 3 3 100.00
chip_sw_sleep_pin_wake 309.180s 5710.191us 3 3 100.00
chip_sw_sleep_pin_retention 3 3 100.00
chip_sw_sleep_pin_retention 313.080s 4385.216us 3 3 100.00
chip_sw_tap_strap_sampling 20 20 100.00
chip_tap_straps_dev 1032.560s 10956.261us 5 5 100.00
chip_tap_straps_testunlock0 524.070s 7144.157us 5 5 100.00
chip_tap_straps_rma 515.640s 6355.522us 5 5 100.00
chip_tap_straps_prod 1174.270s 15131.861us 5 5 100.00
chip_sw_pattgen_ios 3 3 100.00
chip_sw_pattgen_ios 230.230s 3368.843us 3 3 100.00
chip_sw_sleep_pwm_pulses 3 3 100.00
chip_sw_sleep_pwm_pulses 1119.240s 10159.472us 3 3 100.00
chip_sw_data_integrity 6 6 100.00
chip_sw_data_integrity_escalation 720.720s 5802.151us 6 6 100.00
chip_sw_instruction_integrity 6 6 100.00
chip_sw_data_integrity_escalation 720.720s 5802.151us 6 6 100.00
chip_sw_ast_clk_outputs 3 3 100.00
chip_sw_ast_clk_outputs 812.990s 8227.643us 3 3 100.00
chip_sw_ast_clk_rst_inputs 0 3 0.00
chip_sw_ast_clk_rst_inputs 1309.760s 11484.028us 0 3 0.00
chip_sw_ast_sys_clk_jitter 30 30 100.00
chip_sw_flash_ctrl_ops_jitter_en 530.220s 4269.295us 3 3 100.00
chip_sw_flash_ctrl_access_jitter_en 789.550s 6816.650us 3 3 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4758.650s 18843.842us 3 3 100.00
chip_sw_aes_enc_jitter_en 245.630s 3292.772us 3 3 100.00
chip_sw_edn_entropy_reqs_jitter 1041.240s 7134.771us 3 3 100.00
chip_sw_hmac_enc_jitter_en 229.810s 3038.074us 3 3 100.00
chip_sw_keymgr_key_derivation_jitter_en 957.310s 7675.892us 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en 287.060s 3238.148us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 524.060s 4568.338us 3 3 100.00
chip_sw_clkmgr_jitter 195.440s 2899.980us 3 3 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 226.360s 2802.002us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 7 8 87.50
chip_sw_sensor_ctrl_alert 742.010s 8286.291us 4 5 80.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 313.830s 4828.634us 3 3 100.00
chip_sw_sensor_ctrl_ast_status 3 3 100.00
chip_sw_sensor_ctrl_status 272.950s 3267.099us 3 3 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 3 3 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 313.830s 4828.634us 3 3 100.00
chip_sw_smoketest 51 51 100.00
chip_sw_flash_scrambling_smoketest 253.140s 3456.996us 3 3 100.00
chip_sw_aes_smoketest 222.090s 3156.458us 3 3 100.00
chip_sw_aon_timer_smoketest 238.530s 3225.156us 3 3 100.00
chip_sw_clkmgr_smoketest 234.350s 3097.802us 3 3 100.00
chip_sw_csrng_smoketest 181.640s 3267.586us 3 3 100.00
chip_sw_entropy_src_smoketest 1306.740s 7820.659us 3 3 100.00
chip_sw_gpio_smoketest 260.190s 3468.773us 3 3 100.00
chip_sw_hmac_smoketest 256.910s 3519.985us 3 3 100.00
chip_sw_kmac_smoketest 264.040s 3143.339us 3 3 100.00
chip_sw_otbn_smoketest 1890.130s 9963.052us 3 3 100.00
chip_sw_pwrmgr_smoketest 413.520s 6596.656us 3 3 100.00
chip_sw_pwrmgr_usbdev_smoketest 370.870s 6768.971us 3 3 100.00
chip_sw_rv_plic_smoketest 241.730s 3674.110us 3 3 100.00
chip_sw_rv_timer_smoketest 222.060s 3529.627us 3 3 100.00
chip_sw_rstmgr_smoketest 242.400s 2878.445us 3 3 100.00
chip_sw_sram_ctrl_smoketest 197.310s 2749.366us 3 3 100.00
chip_sw_uart_smoketest 246.060s 3388.212us 3 3 100.00
chip_sw_otp_smoketest 3 3 100.00
chip_sw_otp_ctrl_smoketest 240.420s 3264.664us 3 3 100.00
chip_sw_rom_functests 0 3 0.00
rom_keymgr_functest 425.630s 3803.405us 0 3 0.00
chip_sw_boot 3 3 100.00
chip_sw_uart_tx_rx_bootstrap 12426.410s 63236.654us 3 3 100.00
chip_sw_secure_boot 3 3 100.00
rom_e2e_smoke 4063.660s 15460.851us 3 3 100.00
chip_sw_rom_raw_unlock 0 3 0.00
rom_raw_unlock 208.311s 0.000us 0 3 0.00
chip_sw_power_idle_load 0 3 0.00
chip_sw_power_idle_load 289.900s 3821.052us 0 3 0.00
chip_sw_power_sleep_load 0 3 0.00
chip_sw_power_sleep_load 240.630s 2657.696us 0 3 0.00
chip_sw_exit_test_unlocked_bootstrap 3 3 100.00
chip_sw_exit_test_unlocked_bootstrap 11511.470s 55087.894us 3 3 100.00
chip_sw_inject_scramble_seed 3 3 100.00
chip_sw_inject_scramble_seed 12077.650s 59032.064us 3 3 100.00
tl_d_oob_addr_access 0 30 0.00
chip_tl_errors 225.260s 3299.463us 0 30 0.00
tl_d_illegal_access 0 30 0.00
chip_tl_errors 225.260s 3299.463us 0 30 0.00
tl_d_outstanding_access 50 50 100.00
chip_csr_aliasing 7158.340s 39409.152us 5 5 100.00
chip_same_csr_outstanding 4190.420s 30554.083us 20 20 100.00
chip_csr_hw_reset 386.060s 7445.677us 5 5 100.00
chip_csr_rw 626.360s 6247.315us 20 20 100.00
tl_d_partial_access 50 50 100.00
chip_csr_aliasing 7158.340s 39409.152us 5 5 100.00
chip_same_csr_outstanding 4190.420s 30554.083us 20 20 100.00
chip_csr_hw_reset 386.060s 7445.677us 5 5 100.00
chip_csr_rw 626.360s 6247.315us 20 20 100.00
xbar_base_random_sequence 100 100 100.00
xbar_random 99.840s 2465.331us 100 100 100.00
xbar_random_delay 600 600 100.00
xbar_smoke_zero_delays 8.370s 54.722us 100 100 100.00
xbar_smoke_large_delays 107.900s 11205.231us 100 100 100.00
xbar_smoke_slow_rsp 98.630s 5750.313us 100 100 100.00
xbar_random_zero_delays 51.900s 628.994us 100 100 100.00
xbar_random_large_delays 416.280s 55855.327us 100 100 100.00
xbar_random_slow_rsp 490.520s 38724.667us 100 100 100.00
xbar_unmapped_address 200 200 100.00
xbar_unmapped_addr 58.340s 1386.797us 100 100 100.00
xbar_error_and_unmapped_addr 57.480s 1401.668us 100 100 100.00
xbar_error_cases 200 200 100.00
xbar_error_random 82.500s 2334.771us 100 100 100.00
xbar_error_and_unmapped_addr 57.480s 1401.668us 100 100 100.00
xbar_all_access_same_device 200 200 100.00
xbar_access_same_device 127.440s 3612.812us 100 100 100.00
xbar_access_same_device_slow_rsp 1069.510s 85657.045us 100 100 100.00
xbar_all_hosts_use_same_source_id 100 100 100.00
xbar_same_source 83.840s 2699.109us 100 100 100.00
xbar_stress_all 200 200 100.00
xbar_stress_all 554.250s 16138.994us 100 100 100.00
xbar_stress_all_with_error 554.540s 18805.206us 100 100 100.00
xbar_stress_with_reset 200 200 100.00
xbar_stress_all_with_rand_reset 788.450s 19248.210us 100 100 100.00
xbar_stress_all_with_reset_error 730.950s 19493.445us 100 100 100.00
rom_e2e_smoke 3 3 100.00
rom_e2e_smoke 4063.660s 15460.851us 3 3 100.00
rom_e2e_shutdown_output 3 3 100.00
rom_e2e_shutdown_output 3744.060s 30592.173us 3 3 100.00
rom_e2e_shutdown_exception_c 3 3 100.00
rom_e2e_shutdown_exception_c 3776.650s 15023.389us 3 3 100.00
rom_e2e_boot_policy_valid 0 15 0.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 303.040s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 8.846s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 18.323s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 26.868s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 14.615s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 145.184s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 23.915s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 9.903s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 10.811s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 9.594s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 284.599s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 29.565s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 15.869s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 15.891s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 51.420s 0.000us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 30.280s 10.260us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 27.670s 10.220us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 30.010s 10.220us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 24.270s 10.280us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 26.820s 10.280us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 29.390s 10.340us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 20.700s 10.400us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 24.810s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 19.130s 10.140us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 21.200s 10.120us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 30.000s 10.120us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 25.130s 10.300us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 28.120s 10.120us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 30.480s 10.280us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 29.660s 10.300us 0 1 0.00
rom_e2e_asm_init 0 15 0.00
rom_e2e_asm_init_test_unlocked0 235.131s 0.000us 0 3 0.00
rom_e2e_asm_init_dev 95.509s 0.000us 0 3 0.00
rom_e2e_asm_init_prod 17.412s 0.000us 0 3 0.00
rom_e2e_asm_init_prod_end 52.913s 0.000us 0 3 0.00
rom_e2e_asm_init_rma 16.305s 0.000us 0 3 0.00
rom_e2e_keymgr_init 5 9 55.56
rom_e2e_keymgr_init_rom_ext_meas 7511.840s 31647.062us 1 3 33.33
rom_e2e_keymgr_init_rom_ext_no_meas 6993.190s 29316.523us 1 3 33.33
rom_e2e_keymgr_init_rom_ext_invalid_meas 7678.400s 29713.447us 3 3 100.00
rom_e2e_static_critical 3 3 100.00
rom_e2e_static_critical 4230.010s 16656.700us 3 3 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 3 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3600.163s 0.000us 0 3 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 3 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3600.163s 0.000us 0 3 0.00
chip_sw_aes_enc 6 6 100.00
chip_sw_aes_enc 261.270s 2699.536us 3 3 100.00
chip_sw_aes_enc_jitter_en 245.630s 3292.772us 3 3 100.00
chip_sw_aes_entropy 3 3 100.00
chip_sw_aes_entropy 197.030s 3047.843us 3 3 100.00
chip_sw_aes_idle 3 3 100.00
chip_sw_aes_idle 217.560s 3108.857us 3 3 100.00
chip_sw_aes_sideload 3 3 100.00
chip_sw_keymgr_sideload_aes 2098.800s 12455.728us 3 3 100.00
chip_sw_alert_handler_alerts 0 3 0.00
chip_sw_alert_test 246.720s 3064.126us 0 3 0.00
chip_sw_alert_handler_escalations 3 3 100.00
chip_sw_alert_handler_escalation 442.990s 4746.088us 3 3 100.00
chip_sw_all_escalation_resets 96 100 96.00
chip_sw_all_escalation_resets 622.130s 5492.055us 96 100 96.00
chip_sw_alert_handler_irqs 9 9 100.00
chip_plic_all_irqs_0 783.090s 5599.096us 3 3 100.00
chip_plic_all_irqs_10 434.070s 3270.622us 3 3 100.00
chip_plic_all_irqs_20 566.900s 5322.232us 3 3 100.00
chip_sw_alert_handler_entropy 3 3 100.00
chip_sw_alert_handler_entropy 297.570s 3560.824us 3 3 100.00
chip_sw_alert_handler_crashdump 3 3 100.00
chip_sw_rstmgr_alert_info 1415.620s 10143.139us 3 3 100.00
chip_sw_alert_handler_ping_timeout 3 3 100.00
chip_sw_alert_handler_ping_timeout 505.100s 5810.378us 3 3 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 90 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 288.170s 3424.726us 0 90 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 3 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 14400.156s 0.000us 0 3 0.00
chip_sw_alert_handler_lpg_clock_off 3 3 100.00
chip_sw_alert_handler_lpg_clkoff 1323.040s 8012.337us 3 3 100.00
chip_sw_alert_handler_lpg_reset_toggle 3 3 100.00
chip_sw_alert_handler_lpg_reset_toggle 1267.660s 8617.540us 3 3 100.00
chip_sw_alert_handler_ping_ok 3 3 100.00
chip_sw_alert_handler_ping_ok 1054.630s 8222.693us 3 3 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 3 3 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 13092.180s 255092.406us 3 3 100.00
chip_sw_aon_timer_wakeup_irq 3 3 100.00
chip_sw_aon_timer_irq 358.540s 3959.762us 3 3 100.00
chip_sw_aon_timer_sleep_wakeup 3 3 100.00
chip_sw_pwrmgr_smoketest 413.520s 6596.656us 3 3 100.00
chip_sw_aon_timer_wdog_bark_irq 3 3 100.00
chip_sw_aon_timer_irq 358.540s 3959.762us 3 3 100.00
chip_sw_aon_timer_wdog_bite_reset 1 3 33.33
chip_sw_aon_timer_wdog_bite_reset 552.840s 7814.577us 1 3 33.33
chip_sw_aon_timer_sleep_wdog_bite_reset 1 3 33.33
chip_sw_aon_timer_wdog_bite_reset 552.840s 7814.577us 1 3 33.33
chip_sw_aon_timer_sleep_wdog_sleep_pause 5 5 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 433.560s 8435.812us 5 5 100.00
chip_sw_aon_timer_wdog_lc_escalate 3 3 100.00
chip_sw_aon_timer_wdog_lc_escalate 568.950s 5418.191us 3 3 100.00
chip_sw_clkmgr_idle_trans 12 12 100.00
chip_sw_otbn_randomness 792.900s 6271.149us 3 3 100.00
chip_sw_aes_idle 217.560s 3108.857us 3 3 100.00
chip_sw_hmac_enc_idle 264.920s 3368.425us 3 3 100.00
chip_sw_kmac_idle 191.910s 2845.777us 3 3 100.00
chip_sw_clkmgr_off_trans 12 12 100.00
chip_sw_clkmgr_off_aes_trans 458.960s 4370.686us 3 3 100.00
chip_sw_clkmgr_off_hmac_trans 452.770s 5779.007us 3 3 100.00
chip_sw_clkmgr_off_kmac_trans 342.960s 4005.504us 3 3 100.00
chip_sw_clkmgr_off_otbn_trans 423.700s 4477.078us 3 3 100.00
chip_sw_clkmgr_off_peri 3 3 100.00
chip_sw_clkmgr_off_peri 1058.220s 12648.127us 3 3 100.00
chip_sw_clkmgr_div 21 21 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 512.090s 4100.571us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 501.480s 5117.841us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 523.090s 4486.452us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 510.740s 5476.151us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 515.200s 4265.316us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 485.220s 5458.725us 3 3 100.00
chip_sw_ast_clk_outputs 812.990s 8227.643us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_lc 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_lc 721.330s 12884.727us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw 6 6 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 523.090s 4486.452us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 510.740s 5476.151us 3 3 100.00
chip_sw_clkmgr_jitter 30 30 100.00
chip_sw_flash_ctrl_ops_jitter_en 530.220s 4269.295us 3 3 100.00
chip_sw_flash_ctrl_access_jitter_en 789.550s 6816.650us 3 3 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4758.650s 18843.842us 3 3 100.00
chip_sw_aes_enc_jitter_en 245.630s 3292.772us 3 3 100.00
chip_sw_edn_entropy_reqs_jitter 1041.240s 7134.771us 3 3 100.00
chip_sw_hmac_enc_jitter_en 229.810s 3038.074us 3 3 100.00
chip_sw_keymgr_key_derivation_jitter_en 957.310s 7675.892us 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en 287.060s 3238.148us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 524.060s 4568.338us 3 3 100.00
chip_sw_clkmgr_jitter 195.440s 2899.980us 3 3 100.00
chip_sw_clkmgr_extended_range 33 33 100.00
chip_sw_clkmgr_jitter_reduced_freq 203.500s 2575.187us 3 3 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 468.780s 4902.672us 3 3 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 888.960s 7113.678us 3 3 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 4928.930s 24839.601us 3 3 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 264.160s 3155.841us 3 3 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 244.370s 3429.571us 3 3 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 1799.980s 13783.958us 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 258.560s 3769.750us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 532.800s 5084.527us 3 3 100.00
chip_sw_flash_init_reduced_freq 1549.190s 20220.055us 3 3 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 27885.880s 174931.735us 3 3 100.00
chip_sw_clkmgr_deep_sleep_frequency 3 3 100.00
chip_sw_ast_clk_outputs 812.990s 8227.643us 3 3 100.00
chip_sw_clkmgr_sleep_frequency 3 3 100.00
chip_sw_clkmgr_sleep_frequency 527.790s 4991.413us 3 3 100.00
chip_sw_clkmgr_reset_frequency 3 3 100.00
chip_sw_clkmgr_reset_frequency 390.130s 3699.259us 3 3 100.00
chip_sw_clkmgr_escalation_reset 96 100 96.00
chip_sw_all_escalation_resets 622.130s 5492.055us 96 100 96.00
chip_sw_clkmgr_alert_handler_clock_enables 3 3 100.00
chip_sw_alert_handler_lpg_clkoff 1323.040s 8012.337us 3 3 100.00
chip_sw_csrng_edn_cmd 3 3 100.00
chip_sw_entropy_src_csrng 2965.710s 24401.335us 3 3 100.00
chip_sw_csrng_fuse_en_sw_app_read 1 3 33.33
chip_sw_csrng_fuse_en_sw_app_read_test 376.560s 4185.917us 1 3 33.33
chip_sw_csrng_lc_hw_debug_en 3 3 100.00
chip_sw_csrng_lc_hw_debug_en_test 620.730s 7165.092us 3 3 100.00
chip_sw_csrng_known_answer_tests 3 3 100.00
chip_sw_csrng_kat_test 256.000s 3389.831us 3 3 100.00
chip_sw_edn_entropy_reqs 16 16 100.00
chip_sw_csrng_edn_concurrency 6913.570s 31276.508us 10 10 100.00
chip_sw_entropy_src_ast_rng_req 217.740s 2857.232us 3 3 100.00
chip_sw_edn_entropy_reqs 1083.020s 7784.543us 3 3 100.00
chip_sw_entropy_src_ast_rng_req 3 3 100.00
chip_sw_entropy_src_ast_rng_req 217.740s 2857.232us 3 3 100.00
chip_sw_entropy_src_csrng 3 3 100.00
chip_sw_entropy_src_csrng 2965.710s 24401.335us 3 3 100.00
chip_sw_entropy_src_known_answer_tests 3 3 100.00
chip_sw_entropy_src_kat_test 270.780s 3200.601us 3 3 100.00
chip_sw_flash_init 3 3 100.00
chip_sw_flash_init 2038.870s 24988.100us 3 3 100.00
chip_sw_flash_host_access 6 6 100.00
chip_sw_flash_ctrl_access 821.520s 5916.440us 3 3 100.00
chip_sw_flash_ctrl_access_jitter_en 789.550s 6816.650us 3 3 100.00
chip_sw_flash_ctrl_ops 6 6 100.00
chip_sw_flash_ctrl_ops 484.790s 4041.756us 3 3 100.00
chip_sw_flash_ctrl_ops_jitter_en 530.220s 4269.295us 3 3 100.00
chip_sw_flash_rma_unlocked 3 3 100.00
chip_sw_flash_rma_unlocked 4557.180s 43008.878us 3 3 100.00
chip_sw_flash_scramble 3 3 100.00
chip_sw_flash_init 2038.870s 24988.100us 3 3 100.00
chip_sw_flash_idle_low_power 3 3 100.00
chip_sw_flash_ctrl_idle_low_power 359.020s 3837.743us 3 3 100.00
chip_sw_flash_keymgr_seeds 3 3 100.00
chip_sw_keymgr_key_derivation 2385.190s 12662.959us 3 3 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 3 0.00
chip_sw_flash_ctrl_lc_rw_en 242.690s 2483.790us 0 3 0.00
chip_sw_flash_creator_seed_wipe_on_rma 3 3 100.00
chip_sw_flash_rma_unlocked 4557.180s 43008.878us 3 3 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 3 0.00
chip_sw_flash_ctrl_lc_rw_en 242.690s 2483.790us 0 3 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 3 0.00
chip_sw_flash_ctrl_lc_rw_en 242.690s 2483.790us 0 3 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 3 0.00
chip_sw_flash_ctrl_lc_rw_en 242.690s 2483.790us 0 3 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 3 0.00
chip_sw_flash_ctrl_lc_rw_en 242.690s 2483.790us 0 3 0.00
chip_sw_flash_lc_escalate_en 96 100 96.00
chip_sw_all_escalation_resets 622.130s 5492.055us 96 100 96.00
chip_sw_flash_prim_tl_access 3 3 100.00
chip_prim_tl_access 683.340s 14995.733us 3 3 100.00
chip_sw_flash_ctrl_clock_freqs 3 3 100.00
chip_sw_flash_ctrl_clock_freqs 753.060s 5856.673us 3 3 100.00
chip_sw_flash_ctrl_escalation_reset 3 3 100.00
chip_sw_flash_crash_alert 649.890s 6111.591us 3 3 100.00
chip_sw_flash_ctrl_write_clear 3 3 100.00
chip_sw_flash_crash_alert 649.890s 6111.591us 3 3 100.00
chip_sw_hmac_enc 6 6 100.00
chip_sw_hmac_enc 267.740s 2804.171us 3 3 100.00
chip_sw_hmac_enc_jitter_en 229.810s 3038.074us 3 3 100.00
chip_sw_hmac_idle 3 3 100.00
chip_sw_hmac_enc_idle 264.920s 3368.425us 3 3 100.00
chip_sw_hmac_all_configurations 3 3 100.00
chip_sw_hmac_oneshot 1289.130s 7787.774us 3 3 100.00
chip_sw_hmac_multistream_mode 3 3 100.00
chip_sw_hmac_multistream 906.370s 5950.003us 3 3 100.00
chip_sw_i2c_host_tx_rx 9 9 100.00
chip_sw_i2c_host_tx_rx 588.880s 6228.917us 3 3 100.00
chip_sw_i2c_host_tx_rx_idx1 611.670s 5104.814us 3 3 100.00
chip_sw_i2c_host_tx_rx_idx2 535.190s 4906.323us 3 3 100.00
chip_sw_i2c_device_tx_rx 3 3 100.00
chip_sw_i2c_device_tx_rx 425.830s 4463.405us 3 3 100.00
chip_sw_keymgr_key_derivation 6 6 100.00
chip_sw_keymgr_key_derivation 2385.190s 12662.959us 3 3 100.00
chip_sw_keymgr_key_derivation_jitter_en 957.310s 7675.892us 3 3 100.00
chip_sw_keymgr_sideload_kmac 3 3 100.00
chip_sw_keymgr_sideload_kmac 2027.250s 11742.052us 3 3 100.00
chip_sw_keymgr_sideload_aes 3 3 100.00
chip_sw_keymgr_sideload_aes 2098.800s 12455.728us 3 3 100.00
chip_sw_keymgr_sideload_otbn 3 3 100.00
chip_sw_keymgr_sideload_otbn 3360.330s 15464.052us 3 3 100.00
chip_sw_kmac_enc 9 9 100.00
chip_sw_kmac_mode_cshake 264.940s 3456.164us 3 3 100.00
chip_sw_kmac_mode_kmac 256.820s 3601.976us 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en 287.060s 3238.148us 3 3 100.00
chip_sw_kmac_app_keymgr 3 3 100.00
chip_sw_keymgr_key_derivation 2385.190s 12662.959us 3 3 100.00
chip_sw_kmac_app_lc 15 15 100.00
chip_sw_lc_ctrl_transition 946.650s 11518.607us 15 15 100.00
chip_sw_kmac_app_rom 3 3 100.00
chip_sw_kmac_app_rom 210.270s 3179.418us 3 3 100.00
chip_sw_kmac_entropy 3 3 100.00
chip_sw_kmac_entropy 1598.700s 9295.655us 3 3 100.00
chip_sw_kmac_idle 3 3 100.00
chip_sw_kmac_idle 191.910s 2845.777us 3 3 100.00
chip_sw_lc_ctrl_alert_handler_escalation 3 3 100.00
chip_sw_alert_handler_escalation 442.990s 4746.088us 3 3 100.00
chip_sw_lc_ctrl_jtag_access 15 15 100.00
chip_tap_straps_dev 1032.560s 10956.261us 5 5 100.00
chip_tap_straps_rma 515.640s 6355.522us 5 5 100.00
chip_tap_straps_prod 1174.270s 15131.861us 5 5 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 3 3 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 256.240s 3541.986us 3 3 100.00
chip_sw_lc_ctrl_init 15 15 100.00
chip_sw_lc_ctrl_transition 946.650s 11518.607us 15 15 100.00
chip_sw_lc_ctrl_transitions 15 15 100.00
chip_sw_lc_ctrl_transition 946.650s 11518.607us 15 15 100.00
chip_sw_lc_ctrl_kmac_req 15 15 100.00
chip_sw_lc_ctrl_transition 946.650s 11518.607us 15 15 100.00
chip_sw_lc_ctrl_key_div 3 3 100.00
chip_sw_keymgr_key_derivation_prod 1542.690s 10755.142us 3 3 100.00
chip_sw_lc_ctrl_broadcast 76 84 90.48
chip_sw_flash_ctrl_lc_rw_en 242.690s 2483.790us 0 3 0.00
chip_sw_flash_rma_unlocked 4557.180s 43008.878us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 287.510s 3281.672us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_dev 766.520s 7890.338us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_prod 720.910s 5630.566us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_rma 788.770s 7536.258us 0 3 0.00
chip_sw_lc_ctrl_transition 946.650s 11518.607us 15 15 100.00
chip_sw_keymgr_key_derivation 2385.190s 12662.959us 3 3 100.00
chip_sw_rom_ctrl_integrity_check 413.080s 8414.503us 3 3 100.00
chip_sw_sram_ctrl_execution_main 891.080s 10913.406us 3 3 100.00
chip_prim_tl_access 683.340s 14995.733us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_lc 721.330s 12884.727us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 512.090s 4100.571us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 501.480s 5117.841us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 523.090s 4486.452us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 510.740s 5476.151us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 515.200s 4265.316us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 485.220s 5458.725us 3 3 100.00
chip_tap_straps_dev 1032.560s 10956.261us 5 5 100.00
chip_tap_straps_rma 515.640s 6355.522us 5 5 100.00
chip_tap_straps_prod 1174.270s 15131.861us 5 5 100.00
chip_rv_dm_lc_disabled 379.760s 11018.368us 1 3 33.33
chip_lc_scrap 6 6 100.00
chip_sw_lc_ctrl_rma_to_scrap 211.920s 3656.607us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 130.010s 2616.062us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 89.410s 2780.015us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 216.790s 2915.924us 3 3 100.00
chip_lc_test_locked 4 6 66.67
chip_sw_lc_walkthrough_testunlocks 2065.720s 29099.485us 3 3 100.00
chip_rv_dm_lc_disabled 379.760s 11018.368us 1 3 33.33
chip_sw_lc_walkthrough 6 15 40.00
chip_sw_lc_walkthrough_dev 978.360s 11268.767us 0 3 0.00
chip_sw_lc_walkthrough_prod 894.830s 10483.154us 0 3 0.00
chip_sw_lc_walkthrough_prodend 891.010s 11851.925us 3 3 100.00
chip_sw_lc_walkthrough_rma 504.040s 7865.396us 0 3 0.00
chip_sw_lc_walkthrough_testunlocks 2065.720s 29099.485us 3 3 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 5 9 55.56
chip_sw_lc_ctrl_volatile_raw_unlock 99.370s 2941.624us 3 3 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 100.560s 3005.582us 2 3 66.67
rom_volatile_raw_unlock 228.899s 0.000us 0 3 0.00
chip_sw_otbn_op 6 6 100.00
chip_sw_otbn_ecdsa_op_irq 4615.650s 16750.882us 3 3 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4758.650s 18843.842us 3 3 100.00
chip_sw_otbn_rnd_entropy 3 3 100.00
chip_sw_otbn_randomness 792.900s 6271.149us 3 3 100.00
chip_sw_otbn_urnd_entropy 3 3 100.00
chip_sw_otbn_randomness 792.900s 6271.149us 3 3 100.00
chip_sw_otbn_idle 3 3 100.00
chip_sw_otbn_randomness 792.900s 6271.149us 3 3 100.00
chip_sw_otbn_mem_scramble 3 3 100.00
chip_sw_otbn_mem_scramble 422.920s 3645.975us 3 3 100.00
chip_otp_ctrl_init 15 15 100.00
chip_sw_lc_ctrl_transition 946.650s 11518.607us 15 15 100.00
chip_sw_otp_ctrl_keys 15 15 100.00
chip_sw_flash_init 2038.870s 24988.100us 3 3 100.00
chip_sw_otbn_mem_scramble 422.920s 3645.975us 3 3 100.00
chip_sw_keymgr_key_derivation 2385.190s 12662.959us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access 515.220s 5236.118us 3 3 100.00
chip_sw_rv_core_ibex_icache_invalidate 269.420s 3463.625us 3 3 100.00
chip_sw_otp_ctrl_entropy 15 15 100.00
chip_sw_flash_init 2038.870s 24988.100us 3 3 100.00
chip_sw_otbn_mem_scramble 422.920s 3645.975us 3 3 100.00
chip_sw_keymgr_key_derivation 2385.190s 12662.959us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access 515.220s 5236.118us 3 3 100.00
chip_sw_rv_core_ibex_icache_invalidate 269.420s 3463.625us 3 3 100.00
chip_sw_otp_ctrl_program 15 15 100.00
chip_sw_lc_ctrl_transition 946.650s 11518.607us 15 15 100.00
chip_sw_otp_ctrl_program_error 3 3 100.00
chip_sw_lc_ctrl_program_error 515.470s 5085.596us 3 3 100.00
chip_sw_otp_ctrl_hw_cfg0 3 3 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 256.240s 3541.986us 3 3 100.00
chip_sw_otp_ctrl_lc_signals 27 30 90.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 287.510s 3281.672us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_dev 766.520s 7890.338us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_prod 720.910s 5630.566us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_rma 788.770s 7536.258us 0 3 0.00
chip_sw_lc_ctrl_transition 946.650s 11518.607us 15 15 100.00
chip_prim_tl_access 683.340s 14995.733us 3 3 100.00
chip_sw_otp_prim_tl_access 3 3 100.00
chip_prim_tl_access 683.340s 14995.733us 3 3 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1246.360s 7197.982us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 0 3 0.00
chip_sw_pwrmgr_full_aon_reset 149.540s 6829.669us 0 3 0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 3 3 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1599.310s 28360.383us 3 3 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 3 3 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 330.200s 7189.973us 3 3 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 3 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 499.980s 7787.612us 0 3 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 3 3 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 559.650s 5978.385us 3 3 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 3 3 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1455.140s 26680.339us 3 3 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 1 6 16.67
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 621.070s 9549.423us 0 3 0.00
chip_sw_aon_timer_wdog_bite_reset 552.840s 7814.577us 1 3 33.33
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 3 3 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1346.730s 14331.878us 3 3 100.00
chip_sw_pwrmgr_wdog_reset 3 3 100.00
chip_sw_pwrmgr_wdog_reset 486.360s 4285.301us 3 3 100.00
chip_sw_pwrmgr_aon_power_glitch_reset 0 3 0.00
chip_sw_pwrmgr_full_aon_reset 149.540s 6829.669us 0 3 0.00
chip_sw_pwrmgr_main_power_glitch_reset 3 3 100.00
chip_sw_pwrmgr_main_power_glitch_reset 404.390s 4509.721us 3 3 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 3 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 1340.380s 16210.184us 0 3 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 3 3 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 394.010s 6845.189us 3 3 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 0 3 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 223.810s 3078.337us 0 3 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1 3 33.33
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1798.660s 21904.229us 1 3 33.33
chip_sw_pwrmgr_sysrst_ctrl_reset 6 6 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 1102.430s 8786.065us 3 3 100.00
chip_sw_pwrmgr_all_reset_reqs 1657.380s 12965.899us 3 3 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 3 3 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 2610.840s 29558.639us 3 3 100.00
chip_sw_pwrmgr_sleep_disabled 3 3 100.00
chip_sw_pwrmgr_sleep_disabled 242.110s 3371.922us 3 3 100.00
chip_sw_pwrmgr_escalation_reset 96 100 96.00
chip_sw_all_escalation_resets 622.130s 5492.055us 96 100 96.00
chip_sw_rom_access 3 3 100.00
chip_sw_rom_ctrl_integrity_check 413.080s 8414.503us 3 3 100.00
chip_sw_rom_ctrl_integrity_check 3 3 100.00
chip_sw_rom_ctrl_integrity_check 413.080s 8414.503us 3 3 100.00
chip_sw_rstmgr_non_sys_reset_info 10 12 83.33
chip_sw_pwrmgr_all_reset_reqs 1657.380s 12965.899us 3 3 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1798.660s 21904.229us 1 3 33.33
chip_sw_pwrmgr_wdog_reset 486.360s 4285.301us 3 3 100.00
chip_sw_pwrmgr_smoketest 413.520s 6596.656us 3 3 100.00
chip_sw_rstmgr_sys_reset_info 3 3 100.00
chip_rv_dm_ndm_reset_req 411.090s 5343.288us 3 3 100.00
chip_sw_rstmgr_cpu_info 3 3 100.00
chip_sw_rstmgr_cpu_info 530.780s 6796.269us 3 3 100.00
chip_sw_rstmgr_sw_req_reset 3 3 100.00
chip_sw_rstmgr_sw_req 399.930s 4228.967us 3 3 100.00
chip_sw_rstmgr_alert_info 3 3 100.00
chip_sw_rstmgr_alert_info 1415.620s 10143.139us 3 3 100.00
chip_sw_rstmgr_sw_rst 3 3 100.00
chip_sw_rstmgr_sw_rst 230.510s 2595.288us 3 3 100.00
chip_sw_rstmgr_escalation_reset 96 100 96.00
chip_sw_all_escalation_resets 622.130s 5492.055us 96 100 96.00
chip_sw_rstmgr_alert_handler_reset_enables 3 3 100.00
chip_sw_alert_handler_lpg_reset_toggle 1267.660s 8617.540us 3 3 100.00
chip_sw_nmi_irq 3 3 100.00
chip_sw_rv_core_ibex_nmi_irq 635.400s 4786.589us 3 3 100.00
chip_sw_rv_core_ibex_rnd 3 3 100.00
chip_sw_rv_core_ibex_rnd 666.420s 4346.617us 3 3 100.00
chip_sw_rv_core_ibex_address_translation 3 3 100.00
chip_sw_rv_core_ibex_address_translation 239.500s 3182.896us 3 3 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 3 3 100.00
chip_sw_rv_core_ibex_icache_invalidate 269.420s 3463.625us 3 3 100.00
chip_sw_rv_core_ibex_fault_dump 3 3 100.00
chip_sw_rstmgr_cpu_info 530.780s 6796.269us 3 3 100.00
chip_sw_rv_core_ibex_double_fault 3 3 100.00
chip_sw_rstmgr_cpu_info 530.780s 6796.269us 3 3 100.00
chip_jtag_csr_rw 3 3 100.00
chip_jtag_csr_rw 1805.910s 21438.610us 3 3 100.00
chip_jtag_mem_access 3 3 100.00
chip_jtag_mem_access 1192.360s 14596.559us 3 3 100.00
chip_rv_dm_ndm_reset_req 3 3 100.00
chip_rv_dm_ndm_reset_req 411.090s 5343.288us 3 3 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 3 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 262.150s 3331.443us 0 3 0.00
chip_rv_dm_access_after_wakeup 3 3 100.00
chip_sw_rv_dm_access_after_wakeup 390.400s 6837.575us 3 3 100.00
chip_sw_rv_dm_jtag_tap_sel 5 5 100.00
chip_tap_straps_rma 515.640s 6355.522us 5 5 100.00
chip_rv_dm_lc_disabled 1 3 33.33
chip_rv_dm_lc_disabled 379.760s 11018.368us 1 3 33.33
chip_sw_plic_all_irqs 9 9 100.00
chip_plic_all_irqs_0 783.090s 5599.096us 3 3 100.00
chip_plic_all_irqs_10 434.070s 3270.622us 3 3 100.00
chip_plic_all_irqs_20 566.900s 5322.232us 3 3 100.00
chip_sw_plic_sw_irq 3 3 100.00
chip_sw_plic_sw_irq 249.590s 2909.658us 3 3 100.00
chip_sw_timer 3 3 100.00
chip_sw_rv_timer_irq 254.130s 3192.531us 3 3 100.00
chip_sw_spi_device_flash_mode 3 3 100.00
rom_e2e_smoke 4063.660s 15460.851us 3 3 100.00
chip_sw_spi_device_pass_through 3 3 100.00
chip_sw_spi_device_pass_through 539.470s 7323.528us 3 3 100.00
chip_sw_spi_device_pass_through_collision 0 3 0.00
chip_sw_spi_device_pass_through_collision 240.330s 2697.353us 0 3 0.00
chip_sw_spi_device_tpm 3 3 100.00
chip_sw_spi_device_tpm 319.470s 3808.309us 3 3 100.00
chip_sw_spi_host_tx_rx 3 3 100.00
chip_sw_spi_host_tx_rx 273.250s 3040.728us 3 3 100.00
chip_sw_sram_scrambled_access 6 6 100.00
chip_sw_sram_ctrl_scrambled_access 515.220s 5236.118us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 524.060s 4568.338us 3 3 100.00
chip_sw_sleep_sram_ret_contents 6 6 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 497.340s 8394.095us 3 3 100.00
chip_sw_sleep_sram_ret_contents_scramble 537.050s 8245.499us 3 3 100.00
chip_sw_sram_execution 3 3 100.00
chip_sw_sram_ctrl_execution_main 891.080s 10913.406us 3 3 100.00
chip_sw_sram_lc_escalation 102 106 96.23
chip_sw_all_escalation_resets 622.130s 5492.055us 96 100 96.00
chip_sw_data_integrity_escalation 720.720s 5802.151us 6 6 100.00
chip_sw_sysrst_ctrl_reset 5 6 83.33
chip_sw_pwrmgr_sysrst_ctrl_reset 1102.430s 8786.065us 3 3 100.00
chip_sw_sysrst_ctrl_reset 1479.120s 22412.270us 2 3 66.67
chip_sw_sysrst_ctrl_inputs 3 3 100.00
chip_sw_sysrst_ctrl_inputs 250.100s 3633.888us 3 3 100.00
chip_sw_sysrst_ctrl_outputs 3 3 100.00
chip_sw_sysrst_ctrl_outputs 269.680s 3813.738us 3 3 100.00
chip_sw_sysrst_ctrl_in_irq 3 3 100.00
chip_sw_sysrst_ctrl_in_irq 476.910s 4795.743us 3 3 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 2 3 66.67
chip_sw_sysrst_ctrl_reset 1479.120s 22412.270us 2 3 66.67
chip_sw_sysrst_ctrl_sleep_reset 2 3 66.67
chip_sw_sysrst_ctrl_reset 1479.120s 22412.270us 2 3 66.67
chip_sw_sysrst_ctrl_ec_rst_l 3 3 100.00
chip_sw_sysrst_ctrl_ec_rst_l 3093.020s 21017.516us 3 3 100.00
chip_sw_sysrst_ctrl_flash_wp_l 3 3 100.00
chip_sw_sysrst_ctrl_ec_rst_l 3093.020s 21017.516us 3 3 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 3 6 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 471.970s 6912.037us 3 3 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3600.163s 0.000us 0 3 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 163.640s 2546.180us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 232.220s 3110.919us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 363.870s 3677.774us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 437.070s 3709.103us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 1396.920s 8591.858us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 6697.380s 30765.094us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 2504.790s 12323.027us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 193.070s 3262.423us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 3 3 100.00
chip_sw_aes_masking_off 266.110s 3728.418us 3 3 100.00
chip_sw_rv_core_ibex_lockstep_glitch 2 3 66.67
chip_sw_rv_core_ibex_lockstep_glitch 138.230s 3169.890us 2 3 66.67
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 16400.630s 71428.725us 1 1 100.00
chip_sw_power_max_load 3 3 100.00
chip_sw_power_virus 1377.400s 6588.467us 3 3 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 609.910s 6514.347us 0 1 0.00
rom_e2e_jtag_debug_dev 636.830s 7344.249us 0 1 0.00
rom_e2e_jtag_debug_rma 304.250s 3616.021us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 105.090s 3006.008us 0 1 0.00
rom_e2e_jtag_inject_dev 78.040s 1959.121us 0 1 0.00
rom_e2e_jtag_inject_rma 68.570s 2609.432us 0 1 0.00
rom_e2e_self_hash 0 3 0.00
rom_e2e_self_hash 223.316s 0.000us 0 3 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 3 0.00
chip_sw_clkmgr_jitter_frequency 355.070s 3288.123us 0 3 0.00
chip_sw_edn_boot_mode 3 3 100.00
chip_sw_edn_boot_mode 418.790s 2935.436us 3 3 100.00
chip_sw_edn_auto_mode 3 3 100.00
chip_sw_edn_auto_mode 1183.580s 7022.933us 3 3 100.00
chip_sw_edn_sw_mode 3 3 100.00
chip_sw_edn_sw_mode 1616.820s 9961.133us 3 3 100.00
chip_sw_edn_kat 3 3 100.00
chip_sw_edn_kat 290.980s 2997.130us 3 3 100.00
chip_sw_flash_memory_protection 3 3 100.00
chip_sw_flash_ctrl_mem_protection 836.130s 6002.844us 3 3 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 3 3 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 266.490s 3061.106us 3 3 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 221.950s 3188.826us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 3 3 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 417.330s 5996.331us 3 3 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 3 3 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 450.490s 5817.789us 3 3 100.00
chip_sw_all_resets 3 3 100.00
chip_sw_pwrmgr_all_reset_reqs 1657.380s 12965.899us 3 3 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 609.910s 6514.347us 0 1 0.00
rom_e2e_jtag_debug_dev 636.830s 7344.249us 0 1 0.00
rom_e2e_jtag_debug_rma 304.250s 3616.021us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 3 3 100.00
chip_sw_rv_dm_access_after_escalation_reset 573.390s 5218.174us 3 3 100.00
chip_sw_plic_alerts 96 100 96.00
chip_sw_all_escalation_resets 622.130s 5492.055us 96 100 96.00
tick_configuration 0 3 0.00
chip_sw_rv_timer_systick_test 7200.148s 0.000us 0 3 0.00
counter_wrap 0 3 0.00
chip_sw_rv_timer_systick_test 7200.148s 0.000us 0 3 0.00
chip_sw_spi_device_output_when_disabled_or_sleeping 3 3 100.00
chip_sw_spi_device_pinmux_sleep_retention 267.070s 3941.329us 3 3 100.00
chip_sw_uart_watermarks 5 5 100.00
chip_sw_uart_tx_rx 506.000s 4808.973us 5 5 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 4310.650s 19395.905us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 21 28 75.00
chip_sival_flash_info_access 268.100s 3449.325us 3 3 100.00
chip_sw_rstmgr_rst_cnsty_escalation 496.940s 4870.324us 3 3 100.00
chip_sw_otp_ctrl_rot_auth_config 8.270s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 176.480s 3013.013us 3 3 100.00
chip_sw_otp_ctrl_descrambling 262.710s 2828.914us 3 3 100.00
chip_sw_pwrmgr_lowpower_cancel 317.980s 3743.054us 3 3 100.00
chip_sw_pwrmgr_sleep_wake_5_bug 13.281s 0.000us 0 3 0.00
chip_sw_flash_ctrl_write_clear 248.290s 2958.434us 3 3 100.00
ate_bootstrap_flash_erase 9590.790s 45692.517us 3 3 100.00
ate_bootstrap_disjoint 10800.172s 0.000us 0 3 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) 90 test runs
chip_sw_alert_handler_lpg_sleep_mode_alerts 33099979192904324017297851488863005890400018614839764579829438184148054075265 308
UVM_INFO @ 3265.263853 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 68766377172418386480072425141742005559155270236114186442756877740181354797255 308
UVM_INFO @ 2642.629805 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 28386172579991829547838941075154580533685621718735328861601590435863143336592 308
UVM_INFO @ 3356.445730 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 85414933854597156346642077814532421041687924350072014126569276470480491349507 308
UVM_INFO @ 3356.139400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 97253673145993486206305789779233751224828058936376538943967432449773203189501 308
UVM_INFO @ 2901.593646 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 110489575353370757656017517024038092215969714841493333557399579366809881149711 308
UVM_INFO @ 2856.959103 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 68150862481152244760375119255599627814748733975802977256945152397382249611898 308
UVM_INFO @ 3772.487680 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 69116324304148595254376387626533325498694702246237481023489921710524023311111 308
UVM_INFO @ 2874.268740 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 103395142325514600332351912117417273128614049278022273491102776910383594898440 308
UVM_INFO @ 3217.808728 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 82255335331075883267357885433101811674770502031501941371708775434466561001770 308
UVM_INFO @ 2700.119359 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 48982202940866129958561695733176113304225421188067188871211691466456737554846 308
UVM_INFO @ 2885.348816 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 35429163033608948112573403018677767382655593503911439577760584983424643284280 308
UVM_INFO @ 3101.599823 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 42453816663006400164080417663044358655705080580472827845671183440013050224019 308
UVM_INFO @ 2946.375060 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 32163327261524738339872682048441232628400487414444929403175927228795334360051 308
UVM_INFO @ 2795.831532 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 77729874428059387156851653240742478041104130912517978219895834496121449436655 308
UVM_INFO @ 3264.893496 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 21609480619476182265504233394411784106594452934113395918547752026280899019077 308
UVM_INFO @ 2658.369560 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 106926647417933009066333979113412553208613750424544100953292164240510540833718 308
UVM_INFO @ 3257.967485 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 114853000580569601018902665351797226067460613316310930711760807022944634321377 308
UVM_INFO @ 3059.163635 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 6033977483674157872410541194459760986871952889353055796072938968358475763462 308
UVM_INFO @ 3483.090392 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 8425513806146573428204510550275699080369642400677415657746496642132507226638 308
UVM_INFO @ 2933.102306 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 69970636687213070275040678518352541098623464313814936625785464729962591966634 308
UVM_INFO @ 3138.648327 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 100527019520626063408279014512339558877503510816106098816831684172420742044639 308
UVM_INFO @ 3186.900790 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 9826481327007935339126347470547564087723230461470887412726369486907134258691 308
UVM_INFO @ 3319.360125 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 68592343836220798953902550887077216493090110874468966210393107247211919362314 308
UVM_INFO @ 3024.709878 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 30875339193976967316054277779975532853183929203118004431755454017814448409989 308
UVM_INFO @ 3260.073760 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 108947214521161065054315227141540136158252409128946706763179321695343314749396 308
UVM_INFO @ 2839.027312 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 61789792605497475060519349022361376789041843291580550918882848321115178966201 308
UVM_INFO @ 2462.213955 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 62715826889599594594561855196381187971338295322875253030068835099692127566432 308
UVM_INFO @ 3437.943888 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 40893054587949888119516403238942998581723367810049772123836262890633304168012 308
UVM_INFO @ 2935.956500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 14069377140308229630596497461746169002185876793965151801941922694316775034892 308
UVM_INFO @ 2135.947200 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 25978351531538483718699900382248159730073064032485281078585161195816705971317 308
UVM_INFO @ 2656.271483 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 109430180889619098343273936819046820283277383266240263411676180434370713396674 308
UVM_INFO @ 2620.787902 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 24175389691452950098077010958106387252151568828065892673802404715880088232109 308
UVM_INFO @ 3009.213745 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 60963189512429138674301128426702766669923046174883633890696732299972012981854 308
UVM_INFO @ 2858.416860 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 3160688842638773369370567078845802673613536542518348875722994372507046820928 308
UVM_INFO @ 3044.045481 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 34690932158776817316014946946874997110078128938362812775625514968357449030507 308
UVM_INFO @ 2900.676240 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 11774871796233982194618430872066743206741687489645963314572780842291681844781 308
UVM_INFO @ 3021.898426 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 93853454979050019039568010922816708902863790028643597893915254262012081500445 308
UVM_INFO @ 2896.091848 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 40326819734267126459692793478584164742778465055365625496172183874940192629667 308
UVM_INFO @ 2897.673352 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 58149154249837962792791106943999904534504558336908681327846169797360809046676 308
UVM_INFO @ 2521.053850 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 107409978458337160773045465751689919829420024932344077534667429726959429430472 308
UVM_INFO @ 2922.230872 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 33917270416268372967349429272290349870846240112899525014235195742700491164191 308
UVM_INFO @ 3375.146920 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 55103948626179408443209680323633908616696927760566272580284672631196511529241 308
UVM_INFO @ 2823.254828 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 114442112999045515754665610809140074763272602709092281217407779743958201005611 308
UVM_INFO @ 2439.302492 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 86739784176233931867815307626331333024391767880933292869150811891637364622058 308
UVM_INFO @ 3440.274174 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 108465883191854606473215593637981994600174244604185546407336205439260680217226 308
UVM_INFO @ 3192.746023 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 21077968961420146006297231824992930659872069493752727297322975168772513117351 308
UVM_INFO @ 3234.320396 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 55882136520772783127891549184233983283645590220899800100775138363204850686141 308
UVM_INFO @ 2525.039344 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 46285832664142880078601455954631405718911758983016265865211661163169817032647 308
UVM_INFO @ 2829.374050 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 88779117328746779005153626374092382217111843366623630732085734504452695546446 308
UVM_INFO @ 2513.580246 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 71800703080193779244110278094103763556934827615801471632711173261043865341988 308
UVM_INFO @ 2469.296618 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 82243193977273802175508419465085048574356504657761212930918300301941873075854 308
UVM_INFO @ 3078.124700 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 39190150528043991017375930568851144915511342902963612076645802126802004371899 308
UVM_INFO @ 2706.974100 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 68626694963039438727213644897084797680740838040886143695258789214590089605780 308
UVM_INFO @ 2527.721960 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 51959339719640630017356534417170450393880526034810814638831989913630896887800 308
UVM_INFO @ 3193.244254 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 59368201389412978085439929289063329929282440667133167493164614403762905227535 308
UVM_INFO @ 3436.567884 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 60802561655883508798782389366575165111062767889696104636753917953261703995625 308
UVM_INFO @ 2305.483559 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 40393428387199340743575587423488872515790571313572251001810471639299218537601 308
UVM_INFO @ 2659.723430 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 53805551384406359846697804768947682410586101318857473200550455411123901665792 308
UVM_INFO @ 2355.314805 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 6100816801945892054863482296811541319621356390071257892893743722279378917093 308
UVM_INFO @ 3286.242995 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 85556051806638471189644132692796064878725400550560033569457324149645774035734 308
UVM_INFO @ 2765.057480 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 93793145338566796993746824887119242162265763595846866861612770690382784938195 308
UVM_INFO @ 2971.544582 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 31711657087506760928268359987421993363043797249420154004034623789220955675449 308
UVM_INFO @ 2644.387216 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 109591785264996124359876937542777661748677517301702387695122128622796420583710 308
UVM_INFO @ 2736.753971 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 106809777403715850704349066992705828939416866108196517337526286871852761560208 308
UVM_INFO @ 3206.221264 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 33575692434330127584454414155336169714491061464900144713728121014844032154027 308
UVM_INFO @ 2891.505308 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 3537583149923711695975767926674949681010396082457392747373984291397520070842 308
UVM_INFO @ 2867.142204 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 22671240307434582453976990281633157343262635752095904015681555510472156531496 308
UVM_INFO @ 3054.202170 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 86265165997276804035783980022432328181424058796136034572770446067426468510415 308
UVM_INFO @ 2597.887888 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 24418131151628580178936323858902070313331686893663600127517460034331756603957 308
UVM_INFO @ 3282.190555 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 22999061808221753113172622527553779654209533283429620538281477607099119239827 308
UVM_INFO @ 2416.967720 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 35106208184132903581840555888079996230298510561721381182448364255329451088555 308
UVM_INFO @ 2376.815830 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 52702672099416875334640677212887003117289832352926560639317428598064127674957 308
UVM_INFO @ 2595.548776 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 104409157496070502423009364382845895763339015707629546919732372326937371271143 308
UVM_INFO @ 2536.847540 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 102676179937458264757605804931557761023078209781954852951374492519683564909148 308
UVM_INFO @ 2813.531920 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 94489610336851623696123778581518336168154971628296165163545502029244868697496 308
UVM_INFO @ 3503.477644 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 105836678215617431953383683953042661912150301176483447106021615884069647241373 308
UVM_INFO @ 2416.188568 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 111892241764633152240705033993774932715737859009804435661607709114734234923744 308
UVM_INFO @ 3170.089120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 81970591486294419372506670738163927561440614427820793825247089329396392193670 308
UVM_INFO @ 3424.726254 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 84067306193556930354627905107866174925197187158283612782464556796913175942211 308
UVM_INFO @ 3185.583572 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 47897869519995112900205775856578963888118705811802563306672784530494631978133 308
UVM_INFO @ 2317.565016 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 7349908536030920328262417366015401934406076647139660250487715733403206953373 308
UVM_INFO @ 2919.222400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 29403694828300638437608209862153680557478310595173048621817216080124323526937 308
UVM_INFO @ 3230.906152 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 39940200052455416246258433926308079950127777734886100283373531442141962278043 308
UVM_INFO @ 3281.288110 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 22322457967586253552644259108929632274858173666710759809597255829962691397332 308
UVM_INFO @ 2665.180296 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 20930772593111897718777731021039831659947938411750007391803120425570642634660 308
UVM_INFO @ 2839.982224 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 30344276046174341156499332034037565729767316920120500949926407723162413627590 308
UVM_INFO @ 3376.075011 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 52087590583736506482097195337366422673043670226135536610738197584319076708519 308
UVM_INFO @ 3117.853705 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 37678902671532406013440126661204939705149712368846693507144941937480272007707 308
UVM_INFO @ 2657.783860 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 107661952381161383775229628966707482961338648413738410882646888850352604689654 308
UVM_INFO @ 3231.596562 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *). 42 test runs
chip_tl_errors 111699121737029302909612239815275895651574185998449622222444827441957094761888 217
TL item was: req: (cip_tl_seq_item@33016) { a_addr: 'h106a4 a_data: 'h4147e4f8 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3 a_opcode: 'h4 a_user: 'h1ba18 d_param: 'h0 d_source: 'h3 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2924.910472 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 8792660063799162676103885570891708902579778431487375444900125608012856593490 217
TL item was: req: (cip_tl_seq_item@31664) { a_addr: 'h105dc a_data: 'hafe0d62 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2f a_opcode: 'h4 a_user: 'h1b633 d_param: 'h0 d_source: 'h2f d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2547.169885 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 97927188341587052803010357291919554298224418482398261017333374840222440474147 217
TL item was: req: (cip_tl_seq_item@31690) { a_addr: 'h10424 a_data: 'h8bea661f a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h8 a_opcode: 'h4 a_user: 'h181ee d_param: 'h0 d_source: 'h8 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1945.209276 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 60395026162179300622054268782946574188791624671679422852482912381701353609557 224
TL item was: req: (cip_tl_seq_item@32082) { a_addr: 'h10558 a_data: 'h41bea702 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h10 a_opcode: 'h4 a_user: 'h18a34 d_param: 'h0 d_source: 'h10 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2370.728970 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 109361115605263377547288297429075857904763340361934935895696137778362912225512 217
TL item was: req: (cip_tl_seq_item@33576) { a_addr: 'h10344 a_data: 'he42f5e15 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h28 a_opcode: 'h4 a_user: 'h1aed9 d_param: 'h0 d_source: 'h28 d_data: 'hc51513 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd5b a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1846.934735 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 69085070828721247209265857272143912977858917467893024277704261010038906466891 224
TL item was: req: (cip_tl_seq_item@31772) { a_addr: 'h1062c a_data: 'he845e711 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h9 a_opcode: 'h4 a_user: 'h19e05 d_param: 'h0 d_source: 'h9 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2400.858850 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 29386162002997214598569551098472034815202543484547912685384426526361566726041 217
TL item was: req: (cip_tl_seq_item@34606) { a_addr: 'h10784 a_data: 'he2f55793 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1e a_opcode: 'h4 a_user: 'h1a5f1 d_param: 'h0 d_source: 'h1e d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2526.904462 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 46251633233342564828134622261995584626707373532820252454655762032108219347723 224
TL item was: req: (cip_tl_seq_item@32042) { a_addr: 'h10360 a_data: 'hbb1d8022 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1c a_opcode: 'h4 a_user: 'h1bad9 d_param: 'h0 d_source: 'h1c d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2433.707075 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 37577079914033407093981326322512703422151196283093456919722227778631767435585 217
TL item was: req: (cip_tl_seq_item@37306) { a_addr: 'h1073c a_data: 'h17c923d3 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2a a_opcode: 'h4 a_user: 'h1bdf9 d_param: 'h0 d_source: 'h2a d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2326.904670 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 49190850981847159488357884056099801966151738862894920219406689568716488187614 224
TL item was: req: (cip_tl_seq_item@31490) { a_addr: 'h1055c a_data: 'h6ce20bd8 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h11 a_opcode: 'h4 a_user: 'h186ab d_param: 'h0 d_source: 'h11 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1864.554542 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 81421144343417719017568287692784906929894679775788646851901129598352177788269 217
TL item was: req: (cip_tl_seq_item@40572) { a_addr: 'h106a0 a_data: 'h642d5925 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h12 a_opcode: 'h4 a_user: 'h1b6bb d_param: 'h0 d_source: 'h12 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1676.987202 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 60221261938161866201836409103813072959061912431408053049536617344694000349362 217
TL item was: req: (cip_tl_seq_item@31914) { a_addr: 'h10508 a_data: 'h38ee9490 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h29 a_opcode: 'h4 a_user: 'h18626 d_param: 'h0 d_source: 'h29 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1983.815106 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 61457936403238101742698781179639849503947281586589367214840301119795019383192 224
TL item was: req: (cip_tl_seq_item@32460) { a_addr: 'h105f8 a_data: 'h7cd365d0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1b a_opcode: 'h4 a_user: 'h1a224 d_param: 'h0 d_source: 'h1b d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1878.620503 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 69366262219886504803405792580133390081372327191896847863659343827426204772060 217
TL item was: req: (cip_tl_seq_item@36782) { a_addr: 'h10728 a_data: 'h6f01bf84 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2 a_opcode: 'h4 a_user: 'h19584 d_param: 'h0 d_source: 'h2 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2140.746201 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 98139970065991625010353505825457542781689301581925360318731794484666258724150 224
TL item was: req: (cip_tl_seq_item@32526) { a_addr: 'h10408 a_data: 'hbe3a5822 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2 a_opcode: 'h4 a_user: 'h18159 d_param: 'h0 d_source: 'h2 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2362.701786 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 57362600674704822677804095685812463028273883769488128044758971133124503850015 217
TL item was: req: (cip_tl_seq_item@32008) { a_addr: 'h10460 a_data: 'h291f58aa a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2f a_opcode: 'h4 a_user: 'h1a592 d_param: 'h0 d_source: 'h2f d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2392.918391 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 31022551674774288935739335003259516642735962163901905194364589762324623588871 217
TL item was: req: (cip_tl_seq_item@35084) { a_addr: 'h10624 a_data: 'h98804d42 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3d a_opcode: 'h4 a_user: 'h18af5 d_param: 'h0 d_source: 'h3d d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1859.613100 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 81924434877824240645522157005406491754385959939673404154901875034880400237273 217
TL item was: req: (cip_tl_seq_item@39410) { a_addr: 'h105b8 a_data: 'h2218000b a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h17 a_opcode: 'h4 a_user: 'h18a89 d_param: 'h0 d_source: 'h17 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2335.420440 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 71456980082377748478267834474077160240893943395577830511836123023377408848765 224
TL item was: req: (cip_tl_seq_item@33828) { a_addr: 'h10524 a_data: 'h5de8f37 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h7 a_opcode: 'h4 a_user: 'h186b4 d_param: 'h0 d_source: 'h7 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2360.303486 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 94765944950653595476994369073531846893305254041612009710671284280538479127473 217
TL item was: req: (cip_tl_seq_item@34154) { a_addr: 'h10620 a_data: 'h817a13cb a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'he a_opcode: 'h4 a_user: 'h18672 d_param: 'h0 d_source: 'he d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2293.098475 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 75044934741746928867641106069446979189618644819948616216438104259325953181639 217
TL item was: req: (cip_tl_seq_item@40008) { a_addr: 'h10480 a_data: 'h76fbeaf5 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2a a_opcode: 'h4 a_user: 'h1a52e d_param: 'h0 d_source: 'h2a d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2056.333091 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 90673457815286384351368803465203018352725318051822620666975206718820948580422 224
TL item was: req: (cip_tl_seq_item@31604) { a_addr: 'h10428 a_data: 'h599c9bbf a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h18 a_opcode: 'h4 a_user: 'h199b2 d_param: 'h0 d_source: 'h18 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1773.884208 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 1699347092068830843433098924695844854292922366360934522735730893150651313450 217
TL item was: req: (cip_tl_seq_item@32804) { a_addr: 'h105fc a_data: 'h5e08377f a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3 a_opcode: 'h4 a_user: 'h1aeeb d_param: 'h0 d_source: 'h3 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2830.824701 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 16895310394686096107587427900397200185443754907427492725987645250018769420473 224
TL item was: req: (cip_tl_seq_item@31662) { a_addr: 'h104c4 a_data: 'h4df4b71a a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3e a_opcode: 'h4 a_user: 'h18157 d_param: 'h0 d_source: 'h3e d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1981.154468 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 19319106243419675989582504397942577809864377546861255843135739971720372012715 217
TL item was: req: (cip_tl_seq_item@32314) { a_addr: 'h106d4 a_data: 'hc02e25be a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2a a_opcode: 'h4 a_user: 'h1ae97 d_param: 'h0 d_source: 'h2a d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1686.468032 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 53165519186489523062820177798621985866349311821415169319897963741490461389628 224
TL item was: req: (cip_tl_seq_item@31612) { a_addr: 'h105dc a_data: 'h3b4031c2 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h17 a_opcode: 'h4 a_user: 'h1b673 d_param: 'h0 d_source: 'h17 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2711.130120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 63579048350531457167816508477935869512090078284577165916908343809223111820416 218
TL item was: req: (cip_tl_seq_item@176080) { a_addr: 'h10508 a_data: 'h773e87f8 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1b a_opcode: 'h4 a_user: 'h1866d d_param: 'h0 d_source: 'h1b d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 3299.462700 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 12418637722929545018840862176769212981372806073566725111334965849536388220658 217
TL item was: req: (cip_tl_seq_item@34228) { a_addr: 'h10424 a_data: 'hb09e9c48 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h22 a_opcode: 'h4 a_user: 'h181eb d_param: 'h0 d_source: 'h22 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2394.567962 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 60673194906237019309164292999165417330450110288801401015959786638585125547796 217
TL item was: req: (cip_tl_seq_item@32514) { a_addr: 'h107ac a_data: 'h5ad07d58 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1 a_opcode: 'h4 a_user: 'h1a98e d_param: 'h0 d_source: 'h1 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2225.971480 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 20980719956907964987021802138783873237792152890059988613692047397559939841968 224
TL item was: req: (cip_tl_seq_item@32002) { a_addr: 'h10380 a_data: 'hba8d959b a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h7 a_opcode: 'h4 a_user: 'h1ba32 d_param: 'h0 d_source: 'h7 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2256.672205 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 20826071674267557558613307284480599693847671254703840386164310219576474806863 217
TL item was: req: (cip_tl_seq_item@32274) { a_addr: 'h107f8 a_data: 'h33632b75 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h11 a_opcode: 'h4 a_user: 'h1a903 d_param: 'h0 d_source: 'h11 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2504.127848 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 62105706129588336695005565230324970189296535892548442827724874399712444079415 224
TL item was: req: (cip_tl_seq_item@31948) { a_addr: 'h10300 a_data: 'h1e1361e5 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h12 a_opcode: 'h4 a_user: 'h18af4 d_param: 'h0 d_source: 'h12 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2816.052840 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 114285471116227227499515914771280500326083790170582641516937266334876619769830 217
TL item was: req: (cip_tl_seq_item@38998) { a_addr: 'h107e0 a_data: 'hedba1bb7 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3c a_opcode: 'h4 a_user: 'h19933 d_param: 'h0 d_source: 'h3c d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2755.472991 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 102930625920888632918039495260602139473612910279282164893556951782372643135220 217
TL item was: req: (cip_tl_seq_item@33490) { a_addr: 'h10498 a_data: 'h9b4535ef a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h32 a_opcode: 'h4 a_user: 'h19521 d_param: 'h0 d_source: 'h32 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2931.828196 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 16202872255556728492698925395522248167544451638595119546600250229136857554666 217
TL item was: req: (cip_tl_seq_item@33468) { a_addr: 'h10450 a_data: 'h6f503a60 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'he a_opcode: 'h4 a_user: 'h199b7 d_param: 'h0 d_source: 'he d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2377.529348 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 39215689630949837258089959346768383607722938760262062516243030677570790065791 217
TL item was: req: (cip_tl_seq_item@32526) { a_addr: 'h106ac a_data: 'h819bb67 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h29 a_opcode: 'h4 a_user: 'h1aeb0 d_param: 'h0 d_source: 'h29 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2294.015632 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 14155121551178736445868518702977342332752411155477599036223317766074277934031 217
TL item was: req: (cip_tl_seq_item@37996) { a_addr: 'h1052c a_data: 'h91048eb4 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3d a_opcode: 'h4 a_user: 'h19262 d_param: 'h0 d_source: 'h3d d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1756.238142 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 62592736546099330328541841739786886962614970487033678327697126311891368057667 217
TL item was: req: (cip_tl_seq_item@36652) { a_addr: 'h104a0 a_data: 'hfd6d417a a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h13 a_opcode: 'h4 a_user: 'h1bde9 d_param: 'h0 d_source: 'h13 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2093.221380 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 62912081384133184096351392624300269319193885322896418577474820521100933823318 217
TL item was: req: (cip_tl_seq_item@33944) { a_addr: 'h1044c a_data: 'hbc59149a a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h25 a_opcode: 'h4 a_user: 'h1a578 d_param: 'h0 d_source: 'h25 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2500.478962 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 98528447581557245383857849198301504321696552319150018834158423779386155853652 217
TL item was: req: (cip_tl_seq_item@38236) { a_addr: 'h1043c a_data: 'hdb7df930 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h37 a_opcode: 'h4 a_user: 'h1b196 d_param: 'h0 d_source: 'h37 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2726.329580 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 30794892306983066673922856844380642810811890436040892861761890057136754419907 217
TL item was: req: (cip_tl_seq_item@39836) { a_addr: 'h107d4 a_data: 'he01db8b a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h22 a_opcode: 'h4 a_user: 'h1a99f d_param: 'h0 d_source: 'h22 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2517.992665 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 50008848787104867783247137573141805919826687182174080313779998203088606968201 217
TL item was: req: (cip_tl_seq_item@31836) { a_addr: 'h107c0 a_data: 'h8ee8fc66 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h35 a_opcode: 'h4 a_user: 'h18181 d_param: 'h0 d_source: 'h35 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2405.156606 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 42 test runs
chip_sw_pwrmgr_sleep_wake_5_bug 81174296893986034379710524572254486335132775439570852099849805420899945868938 None
---- STDERR ----
Another command (pid=2751230) is running. Waiting for it to complete on the server (server_pid=279994)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 43493280966035531196077367823115132082995127637438728379595692209179455519666 None
Another command (pid=352954) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=394791) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=378214) is running. Waiting for it to complete on the server (server_pid=279994)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_dev 47171809633076973243719821252695885361611749198077121646880435660355679578513 None
---- STDERR ----
Another command (pid=344796) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=399406) is running. Waiting for it to complete on the server (server_pid=279994)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod 42978981612984057806177536382495308504669786006040302588433809478282185959506 None
Another command (pid=423464) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=424277) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=425487) is running. Waiting for it to complete on the server (server_pid=279994)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 89311881478038191506450669946881559562039496607605238037177125170254917969779 None
Another command (pid=436007) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=428411) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=429865) is running. Waiting for it to complete on the server (server_pid=279994)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_rma 64545975036494312624531861456051074638338191702323312989190392002711196717797 None
Another command (pid=420133) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=283010) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=419016) is running. Waiting for it to complete on the server (server_pid=279994)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 55188633091185163318936703959752949957084233819083811487473331773849422849694 None
---- STDERR ----
Another command (pid=279963) is running. Waiting for it to complete on the server (server_pid=279994)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_dev 81504856512150691778193482345494691618965957874904648154371461306602316874650 None
Another command (pid=399559) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=403271) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=366373) is running. Waiting for it to complete on the server (server_pid=279994)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod 41406927232737017612355204405626887834011407727860313423655252892922668543795 None
---- STDERR ----
Another command (pid=384267) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=393961) is running. Waiting for it to complete on the server (server_pid=279994)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 73700284828471471459595318460924720512669387060121424581537335408197168660518 None
Another command (pid=336052) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=282695) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=399133) is running. Waiting for it to complete on the server (server_pid=279994)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_rma 61721451852684481594723360860361116562076129143957630907096675995034654878660 None
Another command (pid=378214) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=282695) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=399133) is running. Waiting for it to complete on the server (server_pid=279994)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 50869488045999711398507176908564811473934290022798835451114428568270996681108 None
Another command (pid=289760) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=361923) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=356983) is running. Waiting for it to complete on the server (server_pid=279994)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_dev 79212548643250997812803554797756183939575160651313722649293864117765197862120 None
---- STDERR ----
Another command (pid=343220) is running. Waiting for it to complete on the server (server_pid=279994)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod 78654751146169943292747297118765713443345415268361297166543690503601789171168 None
Another command (pid=374923) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=381589) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=363977) is running. Waiting for it to complete on the server (server_pid=279994)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 2844110695188916387523336983438632983980272053063552740912236530542324156647 None
---- STDERR ----
Another command (pid=388195) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=280616) is running. Waiting for it to complete on the server (server_pid=279994)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_rma 81343006539816746034400157444158887806690926700407876773136961833314236965301 None
Another command (pid=429865) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=434662) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=414483) is running. Waiting for it to complete on the server (server_pid=279994)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_test_unlocked0 8381383111900518649061853492621470147396155275741050756812291514815518008246 None
Another command (pid=279963) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=282623) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=283532) is running. Waiting for it to complete on the server (server_pid=279994)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_dev 97218300948635987536440839005321209943438967704477491281169460077296768825712 None
Another command (pid=405549) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=404722) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=389339) is running. Waiting for it to complete on the server (server_pid=279994)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod 105172611315713999961279212035902595504869403544241539780314281055390186540973 None
---- STDERR ----
Another command (pid=323620) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=284315) is running. Waiting for it to complete on the server (server_pid=279994)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod_end 70932658763374051503681097590302798207703753674753291431159384104628365849721 None
Another command (pid=358529) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=360358) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=319151) is running. Waiting for it to complete on the server (server_pid=279994)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_rma 52649755863422338263831464706655021467833481128624603596242638237630612315502 None
---- STDERR ----
Another command (pid=319305) is running. Waiting for it to complete on the server (server_pid=279994)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_volatile_raw_unlock 115473535434995544612000857533442216455037431580422464185788869986151873812370 None
Another command (pid=283532) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=284390) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=284096) is running. Waiting for it to complete on the server (server_pid=279994)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_raw_unlock 21355729651830818444928886614917419717414966785021997948274774202484811008720 None
Another command (pid=311789) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=314439) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=291412) is running. Waiting for it to complete on the server (server_pid=279994)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 38786930685280845367009522402205492691567010834731304183952885491908641220071 None
Another command (pid=314439) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=283961) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=315874) is running. Waiting for it to complete on the server (server_pid=279994)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_pwrmgr_sleep_wake_5_bug 18961012663235093910935106039554450387291303854611182092960554349810771173909 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_test_unlocked0 87601427678060763829109856357281719785608030838184267700527826240501760672320 None
Another command (pid=284198) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=289835) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=287770) is running. Waiting for it to complete on the server (server_pid=279994)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_dev 56056729042521780056984155786786488548173952444610124654511344950056495501390 None
Another command (pid=315077) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=416665) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=413515) is running. Waiting for it to complete on the server (server_pid=279994)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod 115219143769262556675624756784307966458574386093241199130846760678453589515807 None
Another command (pid=401099) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=375979) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=426047) is running. Waiting for it to complete on the server (server_pid=279994)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod_end 97305232090642928702783848158862763382358982171940097667914701546888805104471 None
---- STDERR ----
Another command (pid=413358) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=373576) is running. Waiting for it to complete on the server (server_pid=279994)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_rma 95494769945056023814926859174894195014038961196758113049730661047535113347177 None
Another command (pid=427543) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=432992) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=432290) is running. Waiting for it to complete on the server (server_pid=279994)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_volatile_raw_unlock 72227945185708866895864152087141040252850464233047959520238889998713135991690 None
Another command (pid=284823) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=282371) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=284198) is running. Waiting for it to complete on the server (server_pid=279994)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_raw_unlock 10977903431672389771332797553041521252892176591288448988825815216236832222888 None
Another command (pid=279963) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=283532) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=284390) is running. Waiting for it to complete on the server (server_pid=279994)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 54024214369172563554160127495585697216425981872972621346392130345585046924577 None
Another command (pid=289835) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=287770) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=299612) is running. Waiting for it to complete on the server (server_pid=279994)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_pwrmgr_sleep_wake_5_bug 51697322853121606882606683021362598150802654320882110133717344336219698345393 None
---- STDERR ----
Another command (pid=428007) is running. Waiting for it to complete on the server (server_pid=279994)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_test_unlocked0 38922545842244743566102070123682499322899478178793288649090969209838319306847 None
Another command (pid=280616) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=388783) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=390215) is running. Waiting for it to complete on the server (server_pid=279994)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_dev 25896287764133368971317304792547573803938849696612113201706701731487043165417 None
Another command (pid=453068) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=450808) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=453114) is running. Waiting for it to complete on the server (server_pid=279994)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod 78210878487023310823164548532531117837564293004787686851047464147963926308687 None
Another command (pid=381142) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=427543) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=432992) is running. Waiting for it to complete on the server (server_pid=279994)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod_end 56501096651231341477607203964342214519597299636201295713034402170594807654272 None
Another command (pid=400761) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=424065) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=441372) is running. Waiting for it to complete on the server (server_pid=279994)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_rma 45088072834054144271594920187800708643796609684043749843190587708197735582549 None
Another command (pid=428563) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=442852) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=444034) is running. Waiting for it to complete on the server (server_pid=279994)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_volatile_raw_unlock 59534185063674410445263025162578464018775255526443196310099148104441705566860 None
Another command (pid=282695) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=399133) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=401660) is running. Waiting for it to complete on the server (server_pid=279994)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_raw_unlock 39651674218747224647333412559096503911643509159843049863723926235880189407196 None
Another command (pid=284823) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=283351) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=282371) is running. Waiting for it to complete on the server (server_pid=279994)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 3031770536072107677644232791270532517943441768266314662986055812130506981165 None
Another command (pid=279963) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=283532) is running. Waiting for it to complete on the server (server_pid=279994)...
Another command (pid=284390) is running. Waiting for it to complete on the server (server_pid=279994)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Job timed out after * minutes 12 test runs
chip_sw_rv_timer_systick_test 78932137303890398280629620149137964885275204265897133873558384023752571294397 None
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 93513003954439329297768485283840351449470281075345349924231884491918205178844 None
chip_sw_alert_handler_lpg_sleep_mode_pings 115229251688424366776319015564959547445752050153318283024091130234011072294405 None
ate_bootstrap_disjoint 89369068549152200959371100102790245866568431489209084743348487336532636046923 None
chip_sw_rv_timer_systick_test 108308692492231941409989600970179007568423469181074656341987024577609459153595 None
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 110838756515052821933057702683541884711479764243832821463460543369746960005828 None
chip_sw_alert_handler_lpg_sleep_mode_pings 110551472360964518919229433058520917478556820508290533102830164985317965665416 None
ate_bootstrap_disjoint 15660071491175183015471872920907169977420971244200155414648211004860152481460 None
chip_sw_rv_timer_systick_test 36698964112857149513565731499441202549892327726427491400104705945825245949700 None
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 61800030923257548491966766347030487164112919370761664713108659198006211034997 None
chip_sw_alert_handler_lpg_sleep_mode_pings 112281148509632379413110208728316702336601467640096149236214146332440796149721 None
ate_bootstrap_disjoint 85612497981758956429006884098135351831596967883421190330974341006518830613936 None
Offending '(rstreqs[*] && (reset_cause == HwReq))' 11 test runs
chip_sw_pwrmgr_random_sleep_all_reset_reqs 87544905963387212700442746615487001043336111221782153188616290008892603921049 344
UVM_ERROR @ 13415.106000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 13415.106000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 9421055508231175869074451215356489940181047066767289864603441691390536302930 327
UVM_ERROR @ 9549.422500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 9549.422500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 35545784767198998568638094718363487812174820060839921679465030591668329229765 325
UVM_ERROR @ 7787.612000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7787.612000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_all_reset_reqs 13375466240670202437867262651828841907204724523814477223673414662633333149927 315
UVM_ERROR @ 6007.386500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 6007.386500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 55587643853574434842365219517186087446333220399156646629391114568379981644710 314
UVM_ERROR @ 5423.694500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 5423.694500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 76351708030323176010780262180306944737716327515260163640896725591672216480307 325
UVM_ERROR @ 7098.255000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7098.255000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aon_timer_wdog_bite_reset 73075651886193539361764570994729205388077450391668832969724941429851452648770 319
UVM_ERROR @ 7893.478000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7893.478000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 18501553591537700760522304244315234859475263460018028617053695436967566802013 327
UVM_ERROR @ 9657.024500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 9657.024500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 114130152488773508299206387934564356415733330839791183314318764933315069468071 325
UVM_ERROR @ 7116.684000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7116.684000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sysrst_ctrl_reset 27775579644073967743091801892505678322254563402142861358217344890304338107631 334
UVM_ERROR @ 23754.564000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 23754.564000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aon_timer_wdog_bite_reset 35324582399358376020915644557625636465190770885625883400675912451731107025909 319
UVM_ERROR @ 7988.640500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7988.640500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 9 test runs
chip_sw_lc_walkthrough_dev 30473263233600680671451819424871413529249298096659194764742015379710979464206 369
UVM_INFO @ 11463.412073 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 76610115206488399208118229279827705043963834712815888029872414861967726482738 369
UVM_INFO @ 9468.669924 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 85789078771796744092935919340757859428928810827813683994486520247720147034831 341
UVM_INFO @ 7865.396360 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_dev 115032449737753414331764000913184162811611195488242583876934409397835215755565 369
UVM_INFO @ 10042.871212 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 16182636234962738182243063265366207081157129791618105494178994614245203257460 369
UVM_INFO @ 7775.360185 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 112020842655326767901478243750421266051204077590568516989854840397191554364770 341
UVM_INFO @ 5505.382920 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_dev 974827221466146292139975315257802043427293531063744521315221133315679797594 369
UVM_INFO @ 11268.766690 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 12070830806945864283172592252593255212811638823309502214577174064207998388940 369
UVM_INFO @ 10483.153932 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 2915962493196842770179283968331196391355165728681267249638497167896645301983 341
UVM_INFO @ 6776.992808 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[NOA] Null object access 9 test runs
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 16528021523145117014752280018587106002052696762175998254663993278258121684371 327
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 109950190444877648259186641855986327217355092961003006903676692104925968003982 352
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_dev 96421356561730283482981847520499592562296961900298226693243686526269044404310 352
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 90272948369032718936785832039605505785688469695100753559640321060690263270387 319
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 78798091517231723101199821849484048120862402102144965292668165682459410799658 303
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 71318625997771127765534046113001317482904281179260097635776213426936303928070 303
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 55671975084501430799641133704912920146880139264050798710234555002824704281845 303
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 33788489020658713680374476044842441843164156787337219813625779450855086060219 327
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 44107336411117784701187928514834341547980194855020441575151503352877176633932 327
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))' 6 test runs
chip_sw_pwrmgr_sleep_power_glitch_reset 51906420883886603100446249599543314291386746413788547133480532579915926423846 313
UVM_ERROR @ 3086.462278 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 3086.462278 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 105364110042337532156233148365913877064608316660280194041388863874163229759822 327
UVM_ERROR @ 8651.826920 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 8651.826920 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_sleep_power_glitch_reset 53752550523945515625174884390773005354367851979727110308665718272682118389170 313
UVM_ERROR @ 3064.403144 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 3064.403144 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 56976823951348129629420858727100021568878533840741738992739137574675017255662 370
UVM_ERROR @ 16210.184485 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 16210.184485 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_sleep_power_glitch_reset 109291556863729465554968545188371208215602059370835105892353133044140751289328 313
UVM_ERROR @ 3078.336650 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 3078.336650 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 59813712107672093566045978870276339028165195504362526110947760293898799045131 328
UVM_ERROR @ 8784.689000 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 8784.689000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode 6 test runs
rom_e2e_sigverify_always_a_bad_b_bad_prod 976953667518589620964842985632158097701775726279644571299453612391021824575 368
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 52876723645249675918735273192807372290317644620930027493986096051841590644727 368
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 37407881215615844567272590597077644491058758993208813910451363502433214231881 368
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 74930090849300542507484219539879332067522262659996165562475346789749923287078 326
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 114586669572271845010453403866917346997727402651269306420425183660226467991158 325
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 25746288014910364158688041542031288219685797608513174026717655275627795017145 327
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' 4 test runs
chip_sw_otp_ctrl_escalation 21071473111200920996552971311450029268698249018817576278724516417730361093612 316
UVM_ERROR @ 3188.825808 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3188.825808 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_fuse_en_sw_app_read_test 65957962644366375546852915062218241751357799266818291347176793155058204246098 312
UVM_ERROR @ 3256.230746 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3256.230746 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_fuse_en_sw_app_read_test 16485850187630721088972718948160327422702688602914774890823222655241658210036 312
UVM_ERROR @ 3036.517096 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3036.517096 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 36825124658083571644043082117887440499924609700092022746705419643160002557073 317
UVM_ERROR @ 2842.283304 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2842.283304 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty 3 test runs
chip_sw_spi_device_pass_through_collision 75030069637751806564832977445047729779297944118703631809692610714324265092269 320
UVM_INFO @ 2697.352536 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_spi_device_pass_through_collision 65675619982437706874707109708144515665554580074081697277213382572771534958830 320
UVM_INFO @ 3343.059928 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_spi_device_pass_through_collision 736120924620719185639437081459506511171245586022085096295087678362133054544 320
UVM_INFO @ 2894.380690 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 3 test runs
chip_sw_flash_ctrl_lc_rw_en 58614887052703331964086475379655589058117986501140246234965290319679441106674 309
UVM_INFO @ 2483.789822 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_flash_ctrl_lc_rw_en 96975843674941682067407833413758581337931125778519580740719471090950902268196 309
UVM_INFO @ 2839.195812 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_flash_ctrl_lc_rw_en 110721687292752210953358151284358731401262697255672370159939625985474873135282 309
UVM_INFO @ 3177.752750 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * 3 test runs
chip_sw_otp_ctrl_lc_signals_rma 52368648494272520434630127258150433058955805193061671901530103553156799967870 342
UVM_INFO @ 5872.775068 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_otp_ctrl_lc_signals_rma 108634261042118802101187062647691720340436941736057380475556295641902331235068 342
UVM_INFO @ 6568.040080 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_otp_ctrl_lc_signals_rma 81119152515646050897567437006807123424689641855220083359853632481645726937167 342
UVM_INFO @ 7536.257755 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))' 3 test runs
chip_sw_pwrmgr_full_aon_reset 78041182817811889354220217871452095642840607734550289196243517008861912486419 303
UVM_ERROR @ 2418.478568 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 2418.478568 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_full_aon_reset 105843217920675600105502667035214444877618543420838953326363313089652864214953 320
UVM_ERROR @ 6829.668510 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 6829.668510 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_full_aon_reset 57317016754919985502605500771634260786255719138585349922277621231268359867781 303
UVM_ERROR @ 1908.086430 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 1908.086430 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 3 test runs
chip_sw_clkmgr_jitter_frequency 15365329759429555974092792043449089572327687411791345636902186038984299398205 343
UVM_INFO @ 3603.297353 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_jitter_frequency 13643103916788179974897658267757328424901569824575429861532582819470688993547 343
UVM_INFO @ 3703.099430 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_jitter_frequency 90058944158012025057069878707928213134635254620702292620191656111712501738112 343
UVM_INFO @ 3288.122539 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * 3 test runs
chip_sw_power_idle_load 25984018202031634999497929554972657870064979795720945096418978300709874448746 312
UVM_INFO @ 3219.735500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_power_idle_load 33622916883332853663205703673249830280866742132412667109648197338936822013555 312
UVM_INFO @ 3212.622000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_power_idle_load 88163485631712128108627294118116529948304387126964906020793015495636656759327 312
UVM_INFO @ 3821.052000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * 3 test runs
chip_sw_power_sleep_load 58759674501926115377041282177158702284689851816072118024814372917890740577081 318
UVM_INFO @ 3162.832500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_power_sleep_load 77166743667269422076799377259957425348190240323759585865336714567978542488026 318
UVM_INFO @ 2823.690000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_power_sleep_load 57697015429880259851245769352569441187437950278492844649039233486916353845865 318
UVM_INFO @ 2657.696000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = * 3 test runs
chip_sw_ast_clk_rst_inputs 94091659313009949752613354111563376210370503460801425088221219598074052903059 327
UVM_INFO @ 10580.269233 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_ast_clk_rst_inputs 18891964986295253013244314257106673784693116551806469159832147477718277206541 327
UVM_INFO @ 11335.484093 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_ast_clk_rst_inputs 74333529796714730212135492075117851719495429858725001005722535967945486832735 327
UVM_INFO @ 11484.027622 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode 3 test runs
rom_e2e_sigverify_always_a_nothing_b_bad_prod 66931715003844605167518113969973675181410716639274170774013802306041374659264 328
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 104275160630903827149434080509669966005015599155814996405775197232270072356316 326
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 26070458262472089317390115559827279381394770267460738946100321941057066350568 326
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)' 3 test runs
rom_keymgr_functest 106426629920336454158721005712671264305486253106639023172092261483532626619717 327
UVM_ERROR @ 3803.404664 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 3803.404664 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_keymgr_functest 107175488091253339159232405096195979164999251731147437617428568326808327143331 327
UVM_ERROR @ 4185.820484 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 4185.820484 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_keymgr_functest 15450344063587476678251170066730973671203101909378721288545733128825455925801 327
UVM_ERROR @ 4141.231424 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 4141.231424 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:649) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 2 test runs
chip_rv_dm_lc_disabled 63858190331295657707614835256150039725700452444653536055221543225275471058177 236
UVM_INFO @ 5144.126272 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_rv_dm_lc_disabled 93773516558554682098543490118691409445919353135029111931152932412302799245021 216
UVM_INFO @ 2240.007975 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode 2 test runs
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 37593260806410322164426841818708463253626438451378453779099082029353764651991 363
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 44275628131653023839207668838862425836447877559310319118414696934190335957517 326
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode 2 test runs
rom_e2e_sigverify_always_a_bad_b_bad_dev 58865103451483885669169586485871282999317947778510620039394303853072055075694 368
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 3799073463077968684392834314491034166597054720446866726856683755316205924027 328
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns * 2 test runs
rom_e2e_keymgr_init_rom_ext_no_meas 5403813755824635501915176022040957274429447996213185592530505377358624952010 319
UVM_INFO @ 16394.473730 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_keymgr_init_rom_ext_no_meas 47719289849848004244392729238471240384871903871607150699194633996505746294941 319
UVM_INFO @ 18152.638704 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns * 2 test runs
rom_e2e_keymgr_init_rom_ext_meas 10111938616981695366863133932225091983313983836493323519262260390677187149359 319
UVM_INFO @ 16725.381528 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_keymgr_init_rom_ext_meas 97760963312800773895248591206244640381520958030054660329565963670468847745609 319
UVM_INFO @ 16560.907911 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected *, got * 2 test runs
chip_sw_all_escalation_resets 3779772208565599396752446322954535800984243166973743739126961410266284151419 317
UVM_INFO @ 2704.036184 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 48682408851200744200194540697207326872202705108960650987896997708550670090827 317
UVM_INFO @ 2877.648933 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode 1 test run
chip_sw_otp_ctrl_rot_auth_config 106248206163030648760491617440957198669758018728058206801169126559181970551563 282
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:397)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 93602936653689959565932160991588481958507916644694934341665616804593578926072 307
UVM_INFO @ 2364.415815 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(reset_cause == HwReq)' 1 test run
chip_sw_sensor_ctrl_alert 104267794965955174475059982862706213573890882483298488771991606984461976673804 316
UVM_ERROR @ 2592.205970 us: (pwrmgr_rstreqs_sva_if.sv:98) [ASSERT FAILED] SwResetSetCause_A
UVM_INFO @ 2592.205970 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode 1 test run
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 36552619698130928292014336222928955604786177861350700912643943735174364726178 325
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode 1 test run
rom_e2e_sigverify_always_a_nothing_b_bad_dev 104499722826470643572770764897087633458648973213119599989313178343309114956574 328
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:926) [chip_sw_lc_volatile_raw_unlock_vseq] Check failed (!(transition_ctrl & (* << *))) VOLATILE_RAW_UNLOCK is not expected to be supported by this top-level. Check the SecVolatileRawUnlockEn parameter configuration. 1 test run
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 14048830097042322678234879673412340269027309782739492349626541776840548152460 309
UVM_INFO @ 3005.582344 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:547)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 6839210311398392695872774081910296931503823880007739401992038375637792044467 307
UVM_INFO @ 3064.125572 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:738) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. 1 test run
chip_sw_rv_core_ibex_lockstep_glitch 84389880283422351228969553067773004831691975708536952955914498773651458186380 322
UVM_INFO @ 2635.386404 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:502)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 62842068705654928278887496744532180571496431530080583417675426994596459584518 307
UVM_INFO @ 2876.713244 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:912) virtual_sequencer [chip_sw_all_escalation_resets_vseq] Alert usbdev_fatal_fault fired unexpectedly. 1 test run
chip_sw_all_escalation_resets 89675481097880952506698162256917716910028038989980367939425924029865902934338 316
UVM_INFO @ 3639.021374 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---