Simulation Results: clkmgr

 
09/05/2026 22:36:56 DVSim: v1.34.0 sha: f3ee88d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.91 %
  • code
  • 98.66 %
  • assert
  • 95.76 %
  • func
  • 87.31 %
  • line
  • 99.14 %
  • branch
  • 98.90 %
  • cond
  • 96.06 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
92.41%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
clkmgr_smoke 1.390s 87.172us 50 50 100.00
csr_hw_reset 5 5 100.00
clkmgr_csr_hw_reset 1.350s 69.814us 5 5 100.00
csr_rw 20 20 100.00
clkmgr_csr_rw 1.330s 102.964us 20 20 100.00
csr_bit_bash 5 5 100.00
clkmgr_csr_bit_bash 10.430s 1853.496us 5 5 100.00
csr_aliasing 5 5 100.00
clkmgr_csr_aliasing 2.810s 274.627us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.880s 128.217us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
clkmgr_csr_rw 1.330s 102.964us 20 20 100.00
clkmgr_csr_aliasing 2.810s 274.627us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 50 50 100.00
clkmgr_peri 1.280s 57.671us 50 50 100.00
trans_enables 50 50 100.00
clkmgr_trans 1.540s 76.414us 50 50 100.00
extclk 50 50 100.00
clkmgr_extclk 2.290s 296.224us 50 50 100.00
clk_status 50 50 100.00
clkmgr_clk_status 1.350s 149.956us 50 50 100.00
jitter 50 50 100.00
clkmgr_smoke 1.390s 87.172us 50 50 100.00
frequency 50 50 100.00
clkmgr_frequency 15.110s 2238.321us 50 50 100.00
frequency_timeout 50 50 100.00
clkmgr_frequency_timeout 12.670s 2177.098us 50 50 100.00
frequency_overflow 50 50 100.00
clkmgr_frequency 15.110s 2238.321us 50 50 100.00
stress_all 50 50 100.00
clkmgr_stress_all 117.090s 13263.608us 50 50 100.00
alert_test 50 50 100.00
clkmgr_alert_test 1.570s 171.587us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
clkmgr_tl_errors 5.220s 707.456us 20 20 100.00
tl_d_illegal_access 20 20 100.00
clkmgr_tl_errors 5.220s 707.456us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
clkmgr_csr_hw_reset 1.350s 69.814us 5 5 100.00
clkmgr_csr_rw 1.330s 102.964us 20 20 100.00
clkmgr_csr_aliasing 2.810s 274.627us 5 5 100.00
clkmgr_same_csr_outstanding 2.750s 378.582us 20 20 100.00
tl_d_partial_access 50 50 100.00
clkmgr_csr_hw_reset 1.350s 69.814us 5 5 100.00
clkmgr_csr_rw 1.330s 102.964us 20 20 100.00
clkmgr_csr_aliasing 2.810s 274.627us 5 5 100.00
clkmgr_same_csr_outstanding 2.750s 378.582us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 14 25 56.00
clkmgr_sec_cm 26.240s 10015.568us 0 5 0.00
clkmgr_tl_intg_err 47.950s 10019.366us 14 20 70.00
shadow_reg_update_error 10 20 50.00
clkmgr_shadow_reg_errors 1036.000s 200000.000us 10 20 50.00
shadow_reg_read_clear_staged_value 10 20 50.00
clkmgr_shadow_reg_errors 1036.000s 200000.000us 10 20 50.00
shadow_reg_storage_error 10 20 50.00
clkmgr_shadow_reg_errors 1036.000s 200000.000us 10 20 50.00
shadowed_reset_glitch 10 20 50.00
clkmgr_shadow_reg_errors 1036.000s 200000.000us 10 20 50.00
shadow_reg_update_error_with_csr_rw 12 20 60.00
clkmgr_shadow_reg_errors_with_csr_rw 987.130s 200000.000us 12 20 60.00
sec_cm_bus_integrity 14 20 70.00
clkmgr_tl_intg_err 47.950s 10019.366us 14 20 70.00
sec_cm_meas_clk_bkgn_chk 50 50 100.00
clkmgr_frequency 15.110s 2238.321us 50 50 100.00
sec_cm_timeout_clk_bkgn_chk 50 50 100.00
clkmgr_frequency_timeout 12.670s 2177.098us 50 50 100.00
sec_cm_meas_config_shadow 10 20 50.00
clkmgr_shadow_reg_errors 1036.000s 200000.000us 10 20 50.00
sec_cm_idle_intersig_mubi 50 50 100.00
clkmgr_idle_intersig_mubi 2.110s 553.802us 50 50 100.00
sec_cm_lc_ctrl_intersig_mubi 50 50 100.00
clkmgr_lc_ctrl_intersig_mubi 1.580s 150.251us 50 50 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 50 50 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 1.440s 75.910us 50 50 100.00
sec_cm_clk_handshake_intersig_mubi 46 50 92.00
clkmgr_clk_handshake_intersig_mubi 1.310s 57.248us 46 50 92.00
sec_cm_div_intersig_mubi 50 50 100.00
clkmgr_div_intersig_mubi 1.620s 416.132us 50 50 100.00
sec_cm_jitter_config_mubi 20 20 100.00
clkmgr_csr_rw 1.330s 102.964us 20 20 100.00
sec_cm_idle_ctr_redun 0 5 0.00
clkmgr_sec_cm 26.240s 10015.568us 0 5 0.00
sec_cm_meas_config_regwen 20 20 100.00
clkmgr_csr_rw 1.330s 102.964us 20 20 100.00
sec_cm_clk_ctrl_config_regwen 20 20 100.00
clkmgr_csr_rw 1.330s 102.964us 20 20 100.00
prim_count_check 0 5 0.00
clkmgr_sec_cm 26.240s 10015.568us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 50 50 100.00
clkmgr_regwen 8.170s 2492.934us 50 50 100.00
stress_all_with_rand_reset 50 50 100.00
clkmgr_stress_all_with_rand_reset 255.330s 82698.319us 50 50 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 14 test runs
clkmgr_shadow_reg_errors 39234120750031306619214912649452476445498942240765462229209097635487382037007 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 82383231760737507064066171682290351930782869380597612428336879621271571826195 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 69834360035503234223810550886414719040122131759633940323343535061809346038256 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 68813976764698130094200115170338619147781846473552344333092345584052893735091 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 48609304191284782380985663626639186668987538870516269042568643785027960442446 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 77963552185266733648060378910311862503565134226230047906274226144609420940358 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 87035893117696905076718003785001353450229416616415019831257790374471178143230 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 60148402750807950820514303683416630362927972553079691851151512800258509912943 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 92922995556827110932548853465540543666903658819995726304707514946070926860955 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 98105820313859062396156925620496220562575957453504240811814186924456563999228 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 16325157184147451758043425567835999647213666034060197190361698418922346284985 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 67511325173623855256473292731440938954517737031258900224548188912835153219177 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 84646418556420470462794069353041225095408843824174904569987861547185380690220 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 100325761633035364965777655067778496816228771417475192041770409595075078551178 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1030) [clkmgr_common_vseq] timeout wait for alert handshake:fatal_fault 7 test runs
clkmgr_sec_cm 63128125910219910936602101397781801811932979027147678614466404283967014434973 79
UVM_INFO @ 10015567986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 100840974955264868541120933843636732610224225554669860643901396009980683007177 127
UVM_INFO @ 10075728733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 39903309011902230606477286348593187761325631423204093367681432410639865651498 132
UVM_INFO @ 10061229983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 16196771315416217045621686285703580608434882082716344417677886822806831519559 130
UVM_INFO @ 10107470839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 86793844445530245234301346672452881227466210838561590346895118232057844944110 105
UVM_INFO @ 10019366019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 26285162399737025553975821920991863375657569858251062729736838980063525758270 145
UVM_INFO @ 10238924845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 114157472039377343025253874447549359443916023110386049830604882347386886189188 230
UVM_INFO @ 10092081452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire 4 test runs
clkmgr_sec_cm 61364868949142526657417406044713039009993818241132453627297574448719995733383 96
UVM_INFO @ 26265943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 111176591906433854995053015171213637315124207413167377730119431400048256850403 83
UVM_INFO @ 8256383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 32791112991931230576253893915734518805810450911066661865218338140612236229971 85
UVM_INFO @ 10804040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 8994283447709637782384917282490114889726468460356865502329553689784381014073 77
UVM_INFO @ 1749085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_extclk_vseq.sv:99) [clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (* [*] vs * [*]) extclk_status mismatch 4 test runs
clkmgr_clk_handshake_intersig_mubi 104185438933802488990579755095056645622116879215010758173820667205357200755901 74
UVM_INFO @ 8469789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_clk_handshake_intersig_mubi 90581381900199572575861083435514988455853663121856786737066007307693152854574 74
UVM_INFO @ 3697308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_clk_handshake_intersig_mubi 70352358128318232052296211965611575119295645586705805975237986944248252500655 74
UVM_INFO @ 7866500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_clk_handshake_intersig_mubi 72088868154443182511675011751471506953811479385863736035012365544720036955424 74
UVM_INFO @ 25183254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_common_vseq.sv:50) [clkmgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault does not trigger! 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 57991380405100951454121990872239127871698300461123367718285673892004712914781 75
UVM_INFO @ 41043315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:215) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.extclk_status (addr=*) 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 21953542930635100529730491273320661372646904761992781784118358058956123190395 75
UVM_INFO @ 2092844195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:215) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.extclk_ctrl_regwen (addr=*) 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 92879452954192534452500110663559369344554118422731895553147774749188381369846 76
UVM_INFO @ 2368046404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:215) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.clk_enables (addr=*) 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 19959373634212143559004552203083347938904031495403806439836689037949438757953 76
UVM_INFO @ 2333631156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---