Simulation Results: csrng

 
09/05/2026 22:36:56 DVSim: v1.34.0 sha: f3ee88d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.31 %
  • code
  • 96.23 %
  • assert
  • 95.85 %
  • func
  • 90.86 %
  • block
  • 98.59 %
  • line
  • 99.57 %
  • branch
  • 96.46 %
  • toggle
  • 93.64 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
96.60%
V2S
99.63%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
csrng_smoke 35.000s 23.680us 50 50 100.00
csr_hw_reset 5 5 100.00
csrng_csr_hw_reset 34.000s 19.011us 5 5 100.00
csr_rw 20 20 100.00
csrng_csr_rw 34.000s 31.754us 20 20 100.00
csr_bit_bash 5 5 100.00
csrng_csr_bit_bash 63.000s 2575.543us 5 5 100.00
csr_aliasing 5 5 100.00
csrng_csr_aliasing 37.000s 198.401us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
csrng_csr_mem_rw_with_rand_reset 36.000s 116.800us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
csrng_csr_rw 34.000s 31.754us 20 20 100.00
csrng_csr_aliasing 37.000s 198.401us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 200 200 100.00
csrng_intr 37.000s 227.718us 200 200 100.00
alerts 500 500 100.00
csrng_alert 53.000s 4741.484us 500 500 100.00
err 500 500 100.00
csrng_err 34.000s 39.681us 500 500 100.00
cmds 5 50 10.00
csrng_cmds 3601.000s 0.000us 5 50 10.00
life cycle 5 50 10.00
csrng_cmds 3601.000s 0.000us 5 50 10.00
stress_all 45 50 90.00
csrng_stress_all 1126.000s 79665.849us 45 50 90.00
intr_test 50 50 100.00
csrng_intr_test 34.000s 24.519us 50 50 100.00
alert_test 50 50 100.00
csrng_alert_test 34.000s 13.180us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
csrng_tl_errors 35.000s 45.754us 20 20 100.00
tl_d_illegal_access 20 20 100.00
csrng_tl_errors 35.000s 45.754us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
csrng_csr_hw_reset 34.000s 19.011us 5 5 100.00
csrng_csr_rw 34.000s 31.754us 20 20 100.00
csrng_csr_aliasing 37.000s 198.401us 5 5 100.00
csrng_same_csr_outstanding 34.000s 30.270us 20 20 100.00
tl_d_partial_access 50 50 100.00
csrng_csr_hw_reset 34.000s 19.011us 5 5 100.00
csrng_csr_rw 34.000s 31.754us 20 20 100.00
csrng_csr_aliasing 37.000s 198.401us 5 5 100.00
csrng_same_csr_outstanding 34.000s 30.270us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
csrng_sec_cm 35.000s 140.458us 5 5 100.00
csrng_tl_intg_err 38.000s 145.631us 20 20 100.00
sec_cm_config_regwen 70 70 100.00
csrng_regwen 34.000s 37.304us 50 50 100.00
csrng_csr_rw 34.000s 31.754us 20 20 100.00
sec_cm_config_mubi 500 500 100.00
csrng_alert 53.000s 4741.484us 500 500 100.00
sec_cm_intersig_mubi 45 50 90.00
csrng_stress_all 1126.000s 79665.849us 45 50 90.00
sec_cm_main_sm_fsm_sparse 705 705 100.00
csrng_intr 37.000s 227.718us 200 200 100.00
csrng_err 34.000s 39.681us 500 500 100.00
csrng_sec_cm 35.000s 140.458us 5 5 100.00
sec_cm_cmd_stage_fsm_sparse 705 705 100.00
csrng_intr 37.000s 227.718us 200 200 100.00
csrng_err 34.000s 39.681us 500 500 100.00
csrng_sec_cm 35.000s 140.458us 5 5 100.00
sec_cm_ctr_drbg_fsm_sparse 705 705 100.00
csrng_intr 37.000s 227.718us 200 200 100.00
csrng_err 34.000s 39.681us 500 500 100.00
csrng_sec_cm 35.000s 140.458us 5 5 100.00
sec_cm_ctr_drbg_ctr_redun 705 705 100.00
csrng_intr 37.000s 227.718us 200 200 100.00
csrng_err 34.000s 39.681us 500 500 100.00
csrng_sec_cm 35.000s 140.458us 5 5 100.00
sec_cm_gen_cmd_ctr_redun 705 705 100.00
csrng_intr 37.000s 227.718us 200 200 100.00
csrng_err 34.000s 39.681us 500 500 100.00
csrng_sec_cm 35.000s 140.458us 5 5 100.00
sec_cm_ctrl_mubi 500 500 100.00
csrng_alert 53.000s 4741.484us 500 500 100.00
sec_cm_main_sm_ctr_local_esc 700 700 100.00
csrng_intr 37.000s 227.718us 200 200 100.00
csrng_err 34.000s 39.681us 500 500 100.00
sec_cm_constants_lc_gated 45 50 90.00
csrng_stress_all 1126.000s 79665.849us 45 50 90.00
sec_cm_sw_genbits_bus_consistency 500 500 100.00
csrng_alert 53.000s 4741.484us 500 500 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
csrng_tl_intg_err 38.000s 145.631us 20 20 100.00
sec_cm_aes_cipher_fsm_sparse 705 705 100.00
csrng_intr 37.000s 227.718us 200 200 100.00
csrng_err 34.000s 39.681us 500 500 100.00
csrng_sec_cm 35.000s 140.458us 5 5 100.00
sec_cm_aes_cipher_fsm_redun 700 700 100.00
csrng_intr 37.000s 227.718us 200 200 100.00
csrng_err 34.000s 39.681us 500 500 100.00
sec_cm_aes_cipher_ctrl_sparse 700 700 100.00
csrng_intr 37.000s 227.718us 200 200 100.00
csrng_err 34.000s 39.681us 500 500 100.00
sec_cm_aes_cipher_fsm_local_esc 700 700 100.00
csrng_intr 37.000s 227.718us 200 200 100.00
csrng_err 34.000s 39.681us 500 500 100.00
sec_cm_aes_cipher_ctr_redun 705 705 100.00
csrng_intr 37.000s 227.718us 200 200 100.00
csrng_err 34.000s 39.681us 500 500 100.00
csrng_sec_cm 35.000s 140.458us 5 5 100.00
sec_cm_aes_cipher_data_reg_local_esc 700 700 100.00
csrng_intr 37.000s 227.718us 200 200 100.00
csrng_err 34.000s 39.681us 500 500 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 10 0.00
csrng_stress_all_with_rand_reset 10802.165s 0.000us 0 10 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:660) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 42 test runs
csrng_cmds 74312395829623574763171159510872487787329610591545637412985323411979474388762 130
UVM_INFO @ 66695218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 9963166924064255927000709357035240639650399794153920015407031852750802612920 130
UVM_INFO @ 128319109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 18660922550302851697931482999433661904771559708714571323957767284623008666418 130
UVM_INFO @ 40861971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 95860002470206495093174696452506563060493918533627789515364687551574267873351 130
UVM_INFO @ 55736422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 103426222856109155678000757165481191531127259721321993191204100458586698983877 130
UVM_INFO @ 280828681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 23628009325531215876653931358083027551511911667615358048131377261220503997569 140
UVM_INFO @ 439198973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 13165366203314622148303813986707642918420823016690631318064839011311144898207 130
UVM_INFO @ 126997279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 84249467453131711798410978389745404936850649496788385638320085790358732955589 130
UVM_INFO @ 53857372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 92316711555045561637397933326106380693804671483178880561162256937077455445873 130
UVM_INFO @ 291178608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 113788210191744319629205421738980064139456211712834434753567958681399334772120 130
UVM_INFO @ 49195237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 10963341704988651633298497703626085094510757198982243118580611110539461454894 140
UVM_INFO @ 462557709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 71778323604483434269725596606492814387582020063046653475508565964594298466133 130
UVM_INFO @ 148335157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 3380728094696535627237175327798823070832040636001437993232672919497431651899 130
UVM_INFO @ 6667150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 46896463670969767229605417971031411930922065939775463023495330337931917799420 130
UVM_INFO @ 53523037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 13597336201838910881618646906396872996021449796004110424168800798258114213829 130
UVM_INFO @ 226256886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 72445418386224813928851451373400810727108720900619749474172192829972645825763 130
UVM_INFO @ 485374625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 15624915733687084939287244200346980529230797954781318878103593091854602159144 130
UVM_INFO @ 258357867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 49963107484371832302947585898950285572226209197320649543370224290275145366221 130
UVM_INFO @ 160435016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 97455209607581179688127432797127359656704303730849307483456076197010317554336 130
UVM_INFO @ 383535323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 56692303688230508605740050432275994721904119830214118061604279443952052853260 130
UVM_INFO @ 82623848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 5038564126366004121094282965895813928499193509262350124637447271074523429383 140
UVM_INFO @ 1531929215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 30300905293119964634736795374368694104260154767754198905787653687319744675498 130
UVM_INFO @ 526070822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 85724451490263043827763978423458702435132073614545477923854667075662819500693 130
UVM_INFO @ 28649670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 79542750746576847359502404608467865682848196327360908860790615696720200437083 130
UVM_INFO @ 874461854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 14218153541575497159463921312148329367156736277236736331551683085052149758691 130
UVM_INFO @ 57367247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 30852164812835438749675861465691187995599955704431321478299972847545337177099 139
UVM_INFO @ 44316625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 40714482341173176740072439955957694963073216911725680358726011542669050504571 130
UVM_INFO @ 27800565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 98940819007106323029322480542053852315463398890495332545185285485311229804412 130
UVM_INFO @ 271440023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 73151736675617646761289298613077223218516222681589782719517004122667891180031 150
UVM_INFO @ 704359365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 8934757901320062529220474484896555635910315158861974387579222636764258045753 130
UVM_INFO @ 189903349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 3190733208571843870534136804804698571505057897412197687745858559855837485096 130
UVM_INFO @ 91123934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 18227333286011619590548424815323196377669758572120790295936846038135201213023 130
UVM_INFO @ 50692656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 40277567955250620046405084505994819479625968969843031065817555273994600799434 140
UVM_INFO @ 328129273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 25608507085500373228996498727963221315767859021092888202925151207457815823205 130
UVM_INFO @ 143611498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 327714404266901783766205349882860058763930333936469208606489722309241187595 130
UVM_INFO @ 65000572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 56244537531638760588955540894137487302807962851935816634895817470924648113692 130
UVM_INFO @ 163837550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 53599689605699369684403206684098743869558862055023598836708051448978292119929 130
UVM_INFO @ 94474519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 6221469377807882944389342622347105555618031898820750413436060360667305561753 130
UVM_INFO @ 28351788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 4414255846196882951574479465947198436637221584450798280563786287782027502579 130
UVM_INFO @ 47098182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 112918257295373703718795406476641848415532675054756355075722479463245284214884 130
UVM_INFO @ 19989397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 51948660365055178739766491703647349599575014645307259399017605854905160109978 130
UVM_INFO @ 196867030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 11656419552850732923537913073006501164760390191618595096337436784889762617646 130
UVM_INFO @ 101018490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 11 test runs
csrng_stress_all_with_rand_reset 109676937847334153235153778344728925707053599955247594492287222809818121832560 None
csrng_stress_all_with_rand_reset 87081757515726985919734674424412090575684635869230281447739160974410975867761 None
csrng_stress_all_with_rand_reset 101706695531269472648777292382573753187519823610108894797060821471565665036101 None
csrng_stress_all_with_rand_reset 9811537626366129249490758347502589873983307406140820133055474316145687768633 None
csrng_stress_all_with_rand_reset 81045747878116783673126987400156494726674237370614688045681260147589316780716 None
csrng_stress_all_with_rand_reset 34245999732348999381667012725384869750607016111793476691252048906681734464962 None
csrng_stress_all_with_rand_reset 64963403861428785623339599605642566133611858713831809731636834616851522864527 None
csrng_stress_all_with_rand_reset 46071148630526308311104616746626622430378261669953899762306976009323695726460 None
csrng_stress_all_with_rand_reset 103342030319371174563709843660238042022677890472431662886384817101331482857385 None
csrng_cmds 110644575436104120015337617783761837048724182928364379303837015007818197398292 None
csrng_stress_all_with_rand_reset 72790044340484931183286692303405112885114186223536177537250998214125980781191 None
UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq 5 test runs
csrng_stress_all 99285768990709530946542304952261539977645601392250610538129372881401630350176 180
UVM_INFO @ 10747075760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all 106925707736915246189880808015230940785170715972751540359855036687322926172312 143
UVM_INFO @ 12189408092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all 95030389036965862814689959355187482306528809938884954172102310532942145667763 140
UVM_INFO @ 9530051170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all 50378011778112924434188310912964600656416549670070661208056345471835049836119 140
UVM_INFO @ 2644886021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all 15797871742261940108824303974404552049531932790840981658649219864159326627143 146
UVM_INFO @ 4369265443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:418) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: csrng_reg_block.genbits 2 test runs
csrng_cmds 109014925287019664742289479142993815339565701608765316081330728410739516145641 143
UVM_INFO @ 2424913677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 114473767925768702473120485770906711641375113613010317201038530339301610242077 133
UVM_INFO @ 559802417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---