Simulation Results: edn/edn0

 
09/05/2026 22:36:56 DVSim: v1.34.0 sha: f3ee88d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.47 %
  • code
  • 95.94 %
  • assert
  • 97.61 %
  • func
  • 92.86 %
  • line
  • 98.91 %
  • branch
  • 96.51 %
  • cond
  • 94.14 %
  • toggle
  • 97.12 %
  • FSM
  • 93.01 %
Validation stages
V1
100.00%
V2
99.28%
V2S
100.00%
V3
76.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 1.120s 32.232us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 0.940s 29.746us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 1.060s 39.597us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 4.750s 445.805us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 1.280s 48.104us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
edn_csr_mem_rw_with_rand_reset 1.450s 59.783us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 1.060s 39.597us 20 20 100.00
edn_csr_aliasing 1.280s 48.104us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 300 300 100.00
edn_genbits 2.680s 647.800us 300 300 100.00
csrng_commands 300 300 100.00
edn_genbits 2.680s 647.800us 300 300 100.00
genbits 300 300 100.00
edn_genbits 2.680s 647.800us 300 300 100.00
interrupts 50 50 100.00
edn_intr 1.180s 21.856us 50 50 100.00
alerts 200 200 100.00
edn_alert 1.290s 131.954us 200 200 100.00
errs 100 100 100.00
edn_err 1.300s 96.687us 100 100 100.00
disable 93 100 93.00
edn_disable 1.050s 12.536us 50 50 100.00
edn_disable_auto_req_mode 7.770s 500.000us 43 50 86.00
stress_all 50 50 100.00
edn_stress_all 8.950s 448.465us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 0.990s 16.718us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 1.130s 29.496us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 3.260s 290.257us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 3.260s 290.257us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 0.940s 29.746us 5 5 100.00
edn_csr_rw 1.060s 39.597us 20 20 100.00
edn_csr_aliasing 1.280s 48.104us 5 5 100.00
edn_same_csr_outstanding 1.180s 33.011us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 0.940s 29.746us 5 5 100.00
edn_csr_rw 1.060s 39.597us 20 20 100.00
edn_csr_aliasing 1.280s 48.104us 5 5 100.00
edn_same_csr_outstanding 1.180s 33.011us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
edn_sec_cm 7.050s 3189.156us 5 5 100.00
edn_tl_intg_err 2.050s 114.219us 20 20 100.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 1.190s 32.358us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.290s 131.954us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 7.050s 3189.156us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 7.050s 3189.156us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 7.050s 3189.156us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 7.050s 3189.156us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.290s 131.954us 200 200 100.00
edn_sec_cm 7.050s 3189.156us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.290s 131.954us 200 200 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
edn_tl_intg_err 2.050s 114.219us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 38 50 76.00
edn_stress_all_with_rand_reset 136.400s 5604.859us 38 50 76.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 11 test runs
edn_stress_all_with_rand_reset 45066455199463171787108028520502927147038488112795261008475370802658074926328 274
UVM_INFO @ 2752024424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 15462885509416024096227647097772443680509902882456719691924437342834933701152 152
UVM_INFO @ 327207615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 72464279212160119426453655795797022333173299816045482175461079643879878207553 148
UVM_INFO @ 434540534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 69679219784611260038198071620469020016948304162832711902851236197894417434637 119
UVM_INFO @ 443489282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 95081622470471730930760891773565292015848343901916297983417732837603380125670 116
UVM_INFO @ 115893890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 102229847945908825085266347317437623464824572021578981964503155617463650132648 152
UVM_INFO @ 1350925538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 98023166609151576066638298769395861021754266221159133729332247346728946141402 141
UVM_INFO @ 629792676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 41492967583725514717196856713271476192459004244690065094057447172580451644454 203
UVM_INFO @ 1701319428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 11520441564239179840013246280482644267861289372985727633229186483062645618611 155
UVM_INFO @ 736225869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 58364850726753284668439552375350120814128248343660936313244997241812276680170 322
UVM_INFO @ 4075618332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 26464539319946754739270520645184773529346968125807264819314827963817818627583 161
UVM_INFO @ 139632946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 4 test runs
edn_disable_auto_req_mode 3397761090587881530440236199318573991280491879108308033673964035250029011812 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 69229928873426004636480447959247424337349470883640961785577353644725684602110 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 11527051188876140414386869824871359816142893749352921129574639240377465553074 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 36611573288859189527510275546329271142315338393925816073555892826309715566123 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 3 test runs
edn_disable_auto_req_mode 106650881191705179954151760582579088951032361906679031877535284698194212492967 88
UVM_INFO @ 71160553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 37647244949901940551174188506406341295698268363406516053530065977964704765432 88
UVM_INFO @ 57504865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 80991514709339499718563993385680949410346503929848438102527436846506088475878 88
UVM_INFO @ 67990568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [edn_common_vseq] wait timeout occurred! 1 test run
edn_stress_all_with_rand_reset 19985607712859313327386298289995688440718333601032302732417027267110639620726 179
UVM_INFO @ 12327041601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---