Simulation Results: edn/edn1

 
09/05/2026 22:36:56 DVSim: v1.34.0 sha: f3ee88d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.23 %
  • code
  • 96.12 %
  • assert
  • 97.14 %
  • func
  • 92.44 %
  • line
  • 98.48 %
  • branch
  • 94.59 %
  • cond
  • 94.77 %
  • toggle
  • 96.15 %
  • FSM
  • 96.59 %
Validation stages
V1
100.00%
V2
99.48%
V2S
100.00%
V3
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 0.890s 15.928us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 0.830s 29.186us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 0.870s 14.906us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 4.030s 980.864us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 1.230s 67.878us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
edn_csr_mem_rw_with_rand_reset 1.320s 87.595us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 0.870s 14.906us 20 20 100.00
edn_csr_aliasing 1.230s 67.878us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 300 300 100.00
edn_genbits 279.250s 27344.661us 300 300 100.00
csrng_commands 300 300 100.00
edn_genbits 279.250s 27344.661us 300 300 100.00
genbits 300 300 100.00
edn_genbits 279.250s 27344.661us 300 300 100.00
interrupts 50 50 100.00
edn_intr 0.990s 22.764us 50 50 100.00
alerts 200 200 100.00
edn_alert 1.190s 161.222us 200 200 100.00
errs 100 100 100.00
edn_err 1.060s 31.017us 100 100 100.00
disable 95 100 95.00
edn_disable 0.830s 13.305us 50 50 100.00
edn_disable_auto_req_mode 7.120s 500.000us 45 50 90.00
stress_all 50 50 100.00
edn_stress_all 9.070s 448.334us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 0.900s 27.974us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 1.040s 93.814us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 2.340s 1616.736us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 2.340s 1616.736us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 0.830s 29.186us 5 5 100.00
edn_csr_rw 0.870s 14.906us 20 20 100.00
edn_csr_aliasing 1.230s 67.878us 5 5 100.00
edn_same_csr_outstanding 1.160s 36.013us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 0.830s 29.186us 5 5 100.00
edn_csr_rw 0.870s 14.906us 20 20 100.00
edn_csr_aliasing 1.230s 67.878us 5 5 100.00
edn_same_csr_outstanding 1.160s 36.013us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
edn_sec_cm 4.540s 477.845us 5 5 100.00
edn_tl_intg_err 3.290s 278.956us 20 20 100.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 0.890s 18.542us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.190s 161.222us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 4.540s 477.845us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 4.540s 477.845us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 4.540s 477.845us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 4.540s 477.845us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.190s 161.222us 200 200 100.00
edn_sec_cm 4.540s 477.845us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.190s 161.222us 200 200 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
edn_tl_intg_err 3.290s 278.956us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 40 50 80.00
edn_stress_all_with_rand_reset 158.920s 12370.191us 40 50 80.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 7 test runs
edn_stress_all_with_rand_reset 33940431209814792051275115257597359388314262349095019180768222644737113407209 203
UVM_INFO @ 1892646230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 74399850903025437618628560663458673900089077070088439929041897546475039312317 152
UVM_INFO @ 1335924207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 105416091120461332785800682223638371538042068044102319384264159325002908490357 161
UVM_INFO @ 2033496448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 67050114023288753776844467075528140865411114486575648704107585010528235627217 219
UVM_INFO @ 1192398665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 91526814136521278267120321955115647911016437747868805202716593171978179091718 176
UVM_INFO @ 867310795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 96529834232051228616997899104679099029674071524598289927714951076371343643779 302
UVM_INFO @ 1398175150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 6448090880338620332822103619102455303911222575801995109498397166569460133899 135
UVM_INFO @ 1054563099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 5 test runs
edn_disable_auto_req_mode 107085420995369301359953740057350816141377713049663805727652349930956739524404 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 108054797626760623006642187020952213638448278062993749242697880466026491927062 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 70122271722371852081022975018197188515792403119653973542645732015963222302425 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 5249356887787452806365565980532132760508753535207459090412562243431520660300 90
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 95118310408244827939349153343788291937020148762028612600776259530258703454001 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [edn_common_vseq] wait timeout occurred! 2 test runs
edn_stress_all_with_rand_reset 112050696839253689470133782209004846984865618949486836456916072300999457861373 177
UVM_INFO @ 12370190967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 112658514910895453937857566847613133569430439890282154531702965223463046678446 186
UVM_INFO @ 11895983713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1149) [edn_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. 1 test run
edn_stress_all_with_rand_reset 45323965751282156920157730362646144754988275150468687154119066140310978061808 359
UVM_INFO @ 3513965339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---