Simulation Results

Simulation Results: flash_ctrl

09/05/2026 22:36:56 DVSim: v1.34.0 sha: f3ee88d json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
96.99 %

code
95.77 %

assert
96.76 %

func
98.45 %

line
96.09 %

branch
97.40 %

cond
94.85 %

toggle
98.66 %

FSM
91.84 %

Validation stages

V1		99.17%
V2		99.14%
V2S		98.97%
V3		100.00%
unmapped		100.00%

119/120 passed

99.17 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	flash_ctrl_smoke	133.080s	43.080us	50	50	100.00
smoke_hw				5	5	100.00
	flash_ctrl_smoke_hw	24.710s	60.573us	5	5	100.00
csr_hw_reset				5	5	100.00
	flash_ctrl_csr_hw_reset	36.200s	27.174us	5	5	100.00
csr_rw				20	20	100.00
	flash_ctrl_csr_rw	18.070s	83.540us	20	20	100.00
csr_bit_bash				5	5	100.00
	flash_ctrl_csr_bit_bash	69.780s	7671.327us	5	5	100.00
csr_aliasing				5	5	100.00
	flash_ctrl_csr_aliasing	62.400s	3086.968us	5	5	100.00
csr_mem_rw_with_rand_reset				19	20	95.00
	flash_ctrl_csr_mem_rw_with_rand_reset	46.270s	10128.820us	19	20	95.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	flash_ctrl_csr_rw	18.070s	83.540us	20	20	100.00
	flash_ctrl_csr_aliasing	62.400s	3086.968us	5	5	100.00
mem_walk				5	5	100.00
	flash_ctrl_mem_walk	12.630s	233.650us	5	5	100.00
mem_partial_access				5	5	100.00
	flash_ctrl_mem_partial_access	12.920s	50.529us	5	5	100.00

1034/1043 passed

99.14 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
sw_op				5	5	100.00
	flash_ctrl_sw_op	24.670s	42.635us	5	5	100.00
host_read_direct				5	5	100.00
	flash_ctrl_host_dir_rd	57.710s	254.763us	5	5	100.00
rma_hw_if				43	43	100.00
	flash_ctrl_hw_rma	1550.370s	480850.633us	3	3	100.00
	flash_ctrl_hw_rma_reset	835.660s	160177.568us	20	20	100.00
	flash_ctrl_lcmgr_intg	13.400s	73.875us	20	20	100.00
host_controller_arb				5	5	100.00
	flash_ctrl_host_ctrl_arb	1952.150s	230549.214us	5	5	100.00
erase_suspend				5	5	100.00
	flash_ctrl_erase_suspend	336.380s	11230.463us	5	5	100.00
program_reset				30	30	100.00
	flash_ctrl_prog_reset	219.010s	35781.733us	30	30	100.00
full_memory_access				5	5	100.00
	flash_ctrl_full_mem_access	3672.140s	306191.404us	5	5	100.00
rd_buff_eviction				5	5	100.00
	flash_ctrl_rd_buff_evict	137.670s	1361.743us	5	5	100.00
rd_buff_eviction_w_ecc				99	100	99.00
	flash_ctrl_rw_evict	31.060s	27.157us	40	40	100.00
	flash_ctrl_rw_evict_all_en	31.520s	69.354us	39	40	97.50
	flash_ctrl_re_evict	35.730s	73.758us	20	20	100.00
host_arb				20	20	100.00
	flash_ctrl_phy_arb	250.190s	2133.660us	20	20	100.00
host_interleave				20	20	100.00
	flash_ctrl_phy_arb	250.190s	2133.660us	20	20	100.00
memory_protection				20	20	100.00
	flash_ctrl_mp_regions	842.440s	59811.782us	20	20	100.00
fetch_code				10	10	100.00
	flash_ctrl_fetch_code	25.830s	570.746us	10	10	100.00
all_partitions				20	20	100.00
	flash_ctrl_rand_ops	642.550s	1570.611us	20	20	100.00
error_mp				10	10	100.00
	flash_ctrl_error_mp	597.940s	56970.731us	10	10	100.00
error_prog_win				10	10	100.00
	flash_ctrl_error_prog_win	502.290s	3531.847us	10	10	100.00
error_prog_type				5	5	100.00
	flash_ctrl_error_prog_type	1198.870s	573.184us	5	5	100.00
error_read_seed				20	20	100.00
	flash_ctrl_hw_read_seed_err	12.360s	24.378us	20	20	100.00
read_write_overflow				5	5	100.00
	flash_ctrl_oversize_error	205.370s	16734.847us	5	5	100.00
flash_ctrl_disable				50	50	100.00
	flash_ctrl_disable	22.700s	29.948us	50	50	100.00
flash_ctrl_connect				80	80	100.00
	flash_ctrl_connect	17.180s	50.801us	80	80	100.00
stress_all				5	5	100.00
	flash_ctrl_stress_all	689.330s	286.766us	5	5	100.00
secret_partition				130	130	100.00
	flash_ctrl_hw_sec_otp	197.280s	3602.964us	50	50	100.00
	flash_ctrl_otp_reset	111.470s	70.844us	80	80	100.00
isolation_partition				3	3	100.00
	flash_ctrl_hw_rma	1550.370s	480850.633us	3	3	100.00
interrupts				98	100	98.00
	flash_ctrl_intr_rd	232.150s	21029.901us	39	40	97.50
	flash_ctrl_intr_wr	127.240s	35458.714us	10	10	100.00
	flash_ctrl_intr_rd_slow_flash	350.660s	25983.854us	40	40	100.00
	flash_ctrl_intr_wr_slow_flash	3604.012s	0.000us	9	10	90.00
invalid_op				20	20	100.00
	flash_ctrl_invalid_op	78.900s	2105.255us	20	20	100.00
mid_op_rst				5	5	100.00
	flash_ctrl_mid_op_rst	68.820s	960.420us	5	5	100.00
double_bit_err				34	35	97.14
	flash_ctrl_read_word_sweep_derr	21.290s	26.695us	5	5	100.00
	flash_ctrl_ro_derr	113.160s	2576.262us	10	10	100.00
	flash_ctrl_rw_derr	240.880s	4560.909us	10	10	100.00
	flash_ctrl_derr_detect	145.030s	2809.775us	5	5	100.00
	flash_ctrl_integrity	532.400s	6369.558us	4	5	80.00
single_bit_err				25	25	100.00
	flash_ctrl_read_word_sweep_serr	22.580s	87.166us	5	5	100.00
	flash_ctrl_ro_serr	110.970s	1479.947us	10	10	100.00
	flash_ctrl_rw_serr	204.240s	2232.676us	10	10	100.00
singlebit_err_counter				5	5	100.00
	flash_ctrl_serr_counter	76.300s	1024.781us	5	5	100.00
singlebit_err_address				5	5	100.00
	flash_ctrl_serr_address	109.510s	5715.655us	5	5	100.00
scramble				57	62	91.94
	flash_ctrl_wo	3604.010s	0.000us	19	20	95.00
	flash_ctrl_write_word_sweep	9.470s	41.871us	1	1	100.00
	flash_ctrl_read_word_sweep	12.550s	161.730us	1	1	100.00
	flash_ctrl_ro	102.410s	694.166us	18	20	90.00
	flash_ctrl_rw	3604.012s	0.000us	18	20	90.00
filesystem_support				5	5	100.00
	flash_ctrl_fs_sup	39.350s	347.205us	5	5	100.00
rma_write_process_error				23	23	100.00
	flash_ctrl_rma_err	814.830s	104148.351us	3	3	100.00
	flash_ctrl_hw_prog_rma_wipe_err	182.020s	10025.702us	20	20	100.00
alert_test				50	50	100.00
	flash_ctrl_alert_test	13.810s	212.544us	50	50	100.00
intr_test				50	50	100.00
	flash_ctrl_intr_test	13.920s	139.104us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	flash_ctrl_tl_errors	19.650s	231.044us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	flash_ctrl_tl_errors	19.650s	231.044us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	flash_ctrl_csr_hw_reset	36.200s	27.174us	5	5	100.00
	flash_ctrl_csr_rw	18.070s	83.540us	20	20	100.00
	flash_ctrl_csr_aliasing	62.400s	3086.968us	5	5	100.00
	flash_ctrl_same_csr_outstanding	37.140s	650.966us	20	20	100.00
tl_d_partial_access				50	50	100.00
	flash_ctrl_csr_hw_reset	36.200s	27.174us	5	5	100.00
	flash_ctrl_csr_rw	18.070s	83.540us	20	20	100.00
	flash_ctrl_csr_aliasing	62.400s	3086.968us	5	5	100.00
	flash_ctrl_same_csr_outstanding	37.140s	650.966us	20	20	100.00

V2S

480/485 passed

98.97 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
shadow_reg_update_error				20	20	100.00
	flash_ctrl_shadow_reg_errors	60.420s	327.063us	20	20	100.00
shadow_reg_read_clear_staged_value				20	20	100.00
	flash_ctrl_shadow_reg_errors	60.420s	327.063us	20	20	100.00
shadow_reg_storage_error				20	20	100.00
	flash_ctrl_shadow_reg_errors	60.420s	327.063us	20	20	100.00
shadowed_reset_glitch				20	20	100.00
	flash_ctrl_shadow_reg_errors	60.420s	327.063us	20	20	100.00
shadow_reg_update_error_with_csr_rw				20	20	100.00
	flash_ctrl_shadow_reg_errors_with_csr_rw	63.450s	421.008us	20	20	100.00
tl_intg_err				25	25	100.00
	flash_ctrl_sec_cm	2381.560s	3427.085us	5	5	100.00
	flash_ctrl_tl_intg_err	545.020s	762.342us	20	20	100.00
sec_cm_reg_bus_integrity				20	20	100.00
	flash_ctrl_tl_intg_err	545.020s	762.342us	20	20	100.00
sec_cm_host_bus_integrity				20	20	100.00
	flash_ctrl_tl_intg_err	545.020s	762.342us	20	20	100.00
sec_cm_mem_bus_integrity				6	6	100.00
	flash_ctrl_rd_intg	28.220s	613.534us	3	3	100.00
	flash_ctrl_wr_intg	12.110s	369.732us	3	3	100.00
sec_cm_scramble_key_sideload				50	50	100.00
	flash_ctrl_smoke	133.080s	43.080us	50	50	100.00
sec_cm_lc_ctrl_intersig_mubi				260	260	100.00
	flash_ctrl_otp_reset	111.470s	70.844us	80	80	100.00
	flash_ctrl_disable	22.700s	29.948us	50	50	100.00
	flash_ctrl_sec_info_access	75.920s	11872.982us	50	50	100.00
	flash_ctrl_connect	17.180s	50.801us	80	80	100.00
sec_cm_ctrl_config_regwen				5	5	100.00
	flash_ctrl_config_regwen	8.630s	79.407us	5	5	100.00
sec_cm_data_regions_config_regwen				20	20	100.00
	flash_ctrl_csr_rw	18.070s	83.540us	20	20	100.00
sec_cm_data_regions_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	60.420s	327.063us	20	20	100.00
sec_cm_info_regions_config_regwen				20	20	100.00
	flash_ctrl_csr_rw	18.070s	83.540us	20	20	100.00
sec_cm_info_regions_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	60.420s	327.063us	20	20	100.00
sec_cm_bank_config_regwen				20	20	100.00
	flash_ctrl_csr_rw	18.070s	83.540us	20	20	100.00
sec_cm_bank_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	60.420s	327.063us	20	20	100.00
sec_cm_mem_ctrl_global_esc				50	50	100.00
	flash_ctrl_disable	22.700s	29.948us	50	50	100.00
sec_cm_mem_ctrl_local_esc				6	6	100.00
	flash_ctrl_rd_intg	28.220s	613.534us	3	3	100.00
	flash_ctrl_access_after_disable	8.910s	83.293us	3	3	100.00
sec_cm_mem_addr_infection				3	3	100.00
	flash_ctrl_host_addr_infection	28.360s	59.822us	3	3	100.00
sec_cm_mem_disable_config_mubi				50	50	100.00
	flash_ctrl_disable	22.700s	29.948us	50	50	100.00
sec_cm_exec_config_redun				10	10	100.00
	flash_ctrl_fetch_code	25.830s	570.746us	10	10	100.00
sec_cm_mem_scramble				18	20	90.00
	flash_ctrl_rw	3604.012s	0.000us	18	20	90.00
sec_cm_mem_integrity				24	25	96.00
	flash_ctrl_rw_serr	204.240s	2232.676us	10	10	100.00
	flash_ctrl_rw_derr	240.880s	4560.909us	10	10	100.00
	flash_ctrl_integrity	532.400s	6369.558us	4	5	80.00
sec_cm_rma_entry_mem_sec_wipe				3	3	100.00
	flash_ctrl_hw_rma	1550.370s	480850.633us	3	3	100.00
sec_cm_ctrl_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2381.560s	3427.085us	5	5	100.00
sec_cm_phy_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2381.560s	3427.085us	5	5	100.00
sec_cm_phy_prog_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2381.560s	3427.085us	5	5	100.00
sec_cm_ctr_redun				5	5	100.00
	flash_ctrl_sec_cm	2381.560s	3427.085us	5	5	100.00
sec_cm_phy_arbiter_ctrl_redun				5	5	100.00
	flash_ctrl_phy_arb_redun	22.070s	861.189us	5	5	100.00
sec_cm_phy_host_grant_ctrl_consistency				3	5	60.00
	flash_ctrl_phy_host_grant_err	13.080s	22.338us	3	5	60.00
sec_cm_phy_ack_ctrl_consistency				5	5	100.00
	flash_ctrl_phy_ack_consistency	13.870s	23.826us	5	5	100.00
sec_cm_fifo_ctr_redun				5	5	100.00
	flash_ctrl_sec_cm	2381.560s	3427.085us	5	5	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2381.560s	3427.085us	5	5	100.00
sec_cm_prog_tl_lc_gate_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2381.560s	3427.085us	5	5	100.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
asymmetric_read_path				1	1	100.00
	flash_ctrl_rd_ooo	22.350s	194.867us	1	1	100.00

unmapped

3/3 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				3	3	100.00
	flash_ctrl_basic_rw	414.240s	1653.382us	3	3	100.00

Error Messages

	Test	seed	line	log context
Job timed out after * minutes				4 test runs
	flash_ctrl_rw	20920973437338740691748852685196762667408519923190838874861798542145889350272	None
	flash_ctrl_intr_wr_slow_flash	111815124589535584105215419684620459203043595590348339316457751557335079184062	None
	flash_ctrl_rw	98112310068176953534033083487400467579662686135782351844698406471579997403159	None
	flash_ctrl_wo	67234339148555353511365404599487010130622237022420755561118588999867793125220	None
Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))'				2 test runs
	flash_ctrl_phy_host_grant_err	25847399340329467331777688998406246877887048954946955295495803965309894536756	125	UVM_ERROR @ 27931.5 ns: (alert_esc_if.sv:211) [ASSERT FAILED] AlertKnown_A UVM_INFO @ 27931.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_phy_host_grant_err	43265024542505966059104737691257877113800146501701973822030994713461749223629	125	UVM_ERROR @ 7307.5 ns: (alert_esc_if.sv:211) [ASSERT FAILED] AlertKnown_A UVM_INFO @ 7307.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:573) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [] vs [*])				1 test run
	flash_ctrl_integrity	33597254291245136416245635474401869340299114833135949592829096793838645867990	108	UVM_INFO @ 2786895.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [flash_ctrl_common_vseq] wait timeout occurred!				1 test run
	flash_ctrl_csr_mem_rw_with_rand_reset	85605122233942389759381113004377329966638927770676401834680911663173060388507	122	UVM_INFO @ 10128820.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:267) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [] vs [*]) alert recov_err triggered unexpectedly				1 test run
	flash_ctrl_ro	94074176082330081219371527500042324878423948987424222807512669167412135878215	108	UVM_INFO @ 148244.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:267) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [] vs [*]) alert fatal_err triggered unexpectedly				1 test run
	flash_ctrl_ro	14768443248383885183028594840085234071626494685590805663794402815637054106914	108	UVM_INFO @ 184566.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] : obs:exp a4d59d_41e7931b:ffffffff_41e7931b mismatch!!				1 test run
	flash_ctrl_intr_rd	31840465115774410706597685882510652343831144366597486432399246562760896666187	108	UVM_INFO @ 1568472.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: flash_ctrl_core_reg_block.op_status.err reset value:				1 test run
	flash_ctrl_rw_evict_all_en	87482107142207653252750488867058350427271436450084272091439084683370960961638	108	UVM_INFO @ 22920.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---