Simulation Results: gpio

 
09/05/2026 22:36:56 DVSim: v1.34.0 sha: f3ee88d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.36 %
  • code
  • 98.23 %
  • assert
  • 96.84 %
  • func
  • 100.00 %
  • line
  • 99.76 %
  • branch
  • 99.80 %
  • cond
  • 99.42 %
  • toggle
  • 93.94 %
Validation stages
V1
100.00%
V2
93.43%
V2S
100.00%
V3
39.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 200 200 100.00
gpio_smoke 1.700s 134.140us 50 50 100.00
gpio_smoke_no_pullup_pulldown 1.970s 107.126us 50 50 100.00
gpio_smoke_en_cdc_prim 1.900s 84.085us 50 50 100.00
gpio_smoke_no_pullup_pulldown_en_cdc_prim 1.670s 51.093us 50 50 100.00
csr_hw_reset 5 5 100.00
gpio_csr_hw_reset 0.970s 67.187us 5 5 100.00
csr_rw 20 20 100.00
gpio_csr_rw 1.000s 17.305us 20 20 100.00
csr_bit_bash 5 5 100.00
gpio_csr_bit_bash 3.450s 82.284us 5 5 100.00
csr_aliasing 5 5 100.00
gpio_csr_aliasing 1.090s 122.542us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
gpio_csr_mem_rw_with_rand_reset 1.890s 43.836us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
gpio_csr_rw 1.000s 17.305us 20 20 100.00
gpio_csr_aliasing 1.090s 122.542us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
direct_and_masked_out 100 100 100.00
gpio_random_dout_din 1.650s 199.224us 50 50 100.00
gpio_random_dout_din_no_pullup_pulldown 1.660s 211.442us 50 50 100.00
out_in_regs_read_write 50 50 100.00
gpio_dout_din_regs_random_rw 1.340s 50.162us 50 50 100.00
gpio_interrupt_programming 50 50 100.00
gpio_intr_rand_pgm 1.800s 420.424us 50 50 100.00
random_interrupt_trigger 50 50 100.00
gpio_rand_intr_trigger 4.100s 130.718us 50 50 100.00
interrupt_and_noise_filter 50 50 100.00
gpio_intr_with_filter_rand_intr_event 3.230s 89.377us 50 50 100.00
noise_filter_stress 50 50 100.00
gpio_filter_stress 20.680s 2390.690us 50 50 100.00
regs_long_reads_and_writes 50 50 100.00
gpio_random_long_reg_writes_reg_reads 6.380s 147.724us 50 50 100.00
full_random 50 50 100.00
gpio_full_random 1.420s 66.327us 50 50 100.00
stress_all 6 50 12.00
gpio_stress_all 106.180s 8854.876us 6 50 12.00
alert_test 50 50 100.00
gpio_alert_test 0.940s 16.812us 50 50 100.00
intr_test 50 50 100.00
gpio_intr_test 0.980s 17.040us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
gpio_tl_errors 3.550s 671.409us 20 20 100.00
tl_d_illegal_access 20 20 100.00
gpio_tl_errors 3.550s 671.409us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
gpio_csr_rw 1.000s 17.305us 20 20 100.00
gpio_same_csr_outstanding 1.280s 145.151us 20 20 100.00
gpio_csr_aliasing 1.090s 122.542us 5 5 100.00
gpio_csr_hw_reset 0.970s 67.187us 5 5 100.00
tl_d_partial_access 50 50 100.00
gpio_csr_rw 1.000s 17.305us 20 20 100.00
gpio_same_csr_outstanding 1.280s 145.151us 20 20 100.00
gpio_csr_aliasing 1.090s 122.542us 5 5 100.00
gpio_csr_hw_reset 0.970s 67.187us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
gpio_tl_intg_err 1.890s 132.565us 20 20 100.00
gpio_sec_cm 1.410s 372.698us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
gpio_tl_intg_err 1.890s 132.565us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
straps_data 39 50 78.00
gpio_rand_straps 0.950s 15.293us 39 50 78.00
stress_all_with_rand_reset 0 50 0.00
gpio_stress_all_with_rand_reset 24.980s 2277.498us 0 50 0.00

Error Messages

   Test seed line log context
UVM_ERROR (gpio_scoreboard.sv:216) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 55 test runs
gpio_stress_all 65142478011124284948749886987446160156314245506762227825399637329340988743510 594
UVM_INFO @ 844425560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 58465248108959281962406283982347257008436201373381717742718160506977418483926 779
UVM_INFO @ 910163256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 57572082429484365806022582663362885779317623470508073854288174889561314773421 76
UVM_INFO @ 4234847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 55214229614586209400373120198509912332501261440100687685536978723360189512334 470
UVM_INFO @ 2720215153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 17921294298349691644815392788999299371538994679403110724505718465017551462367 75
UVM_INFO @ 19949404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 98060032556109065681753472778399718934883510056385164474948835001945018526753 129
UVM_INFO @ 256798696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 86689876527077218930936526888892466879693253836123825577564348562414228380005 595
UVM_INFO @ 788692799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 85839298309944149214005009523601044313491434663433171532193299914278666825782 1039
UVM_INFO @ 2343754402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 92576524862120015421856171333929078431497160092160393357296339775179894233651 75
UVM_INFO @ 718192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 47099477312362003161360335426400902954185482837962450452808475538566875174515 76
UVM_INFO @ 4319109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 95199351053363079108249180070030243891445897600753543783737526923821659421317 246
UVM_INFO @ 555604613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 47572332639516271898037623550101626895081264517301608619130550942145477544145 1189
UVM_INFO @ 2781184765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 38889584793412449994610480242901352537032634995913212037689883585587268594569 157
UVM_INFO @ 1062257441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 37115326821402598366432472929821919247187097904896730889853498952765477576021 75
UVM_INFO @ 1490489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 90267942973566473261701205625698919323710799790152796484696837716003729572911 445
UVM_INFO @ 4452237781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 106269633792006636925554009311189555269106408203507082205806702570065195618100 326
UVM_INFO @ 561808614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 4476384415514849622748082117140979255248374730829732739925803492694284165687 2416
UVM_INFO @ 31420665966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 11498292914210463829674417805692766336234432742200463702114101621603274614632 1797
UVM_INFO @ 1870485550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 75864654437923918711080252612872572714702070470956510863487447110284792088464 75
UVM_INFO @ 5034704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 63070917736739042010952012556358144990591889762041749835082208243747131412074 76
UVM_INFO @ 143368642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 64999803835926272504795293823983458580648199651586615970207580209927378536731 75
UVM_INFO @ 5447690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 14433836713481683450335620004520111395906437566783918918612643823830923151598 450
UVM_INFO @ 10385377841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 49907796445288491628433946383915789542625845767441730635312728861705793731861 588
UVM_INFO @ 3440963168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 61302000241220144537989246568952175849672138815131439361411733421589738411203 192
UVM_INFO @ 170718969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 105525797652035614848625164644255775786879053042079915868666754596597047209918 79
UVM_INFO @ 2215758156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 72002965542928210445060465366428423386568285279823845759823273317038172211017 78
UVM_INFO @ 1260579831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 80473215215574922388946143567555653767746516844286904626262313411027128612306 75
UVM_INFO @ 1408898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 68216117616643979475781662035730586362577081040426433895410074814427156673148 468
UVM_INFO @ 808271841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 17442977465892462148791960050018410113547400860184119317208394209244716864627 75
UVM_INFO @ 4138144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 53807066989990712999083655817788963870019617836408603164380567180126145234196 917
UVM_INFO @ 753848028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 38748183234879727594569493588239168219064569839350811683993231147492253318169 1827
UVM_INFO @ 5028211612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 108661437013307851838348490808747363544116055637598813238043630522534118674232 75
UVM_INFO @ 1198853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 57002604561000255498890172773438160789264520395181789437067127062600630835125 963
UVM_INFO @ 16065885589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 7456976561742845520496873020082567320232598543502161468956930530777367776050 1967
UVM_INFO @ 5050820630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 27993832093174197680759987737606367027696865720414370348221477384491486959530 1855
UVM_INFO @ 13442719856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 63547525691821741998514271600665325670705130458442765430516566176954174617076 75
UVM_INFO @ 2309026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 28736620741035052312552251147278222049841850914955319811673982640437144353453 1224
UVM_INFO @ 17160303137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 41616939838632691345572817009747487392987526396002765548662855788334275108766 854
UVM_INFO @ 4621062064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 52649488063725129529697603497594661946829253477449332964326891732878760322743 3488
UVM_INFO @ 8854876131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 71443804173066535617401575972744407169832316489286036631627776122221769524944 77
UVM_INFO @ 3038027568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 71003388958162032757554481353514027211959013669740419938909279664275476212313 472
UVM_INFO @ 5110377571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 68258053241459724437563998717674504379440042386077137696535776724026107549347 75
UVM_INFO @ 1063590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 63355651848528797130536584976348704874615433152291118432859762347112735639701 334
UVM_INFO @ 525707074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 12820185123506310981504853597455939145201521192061728261091219963630893549512 75
UVM_INFO @ 4732598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 48121281263463342983481927790611149631251746321103627367298385008412769729959 807
UVM_INFO @ 644656768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 55088857073569305366665401396745567767230015671791833794940101004483737055362 1282
UVM_INFO @ 6995195364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 9486254247296658561863666189671292574374898729080082378333124239089434938592 611
UVM_INFO @ 9000126014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 53164961376066912964142844643958165403355719386878922552297486299014489625940 80
UVM_INFO @ 222662393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 101213044128705762997661001713384803757849786577877989189471180515892717473848 1376
UVM_INFO @ 11005212605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 74027015909084757358816686631544168681684627286255872928799849174714622043389 835
UVM_INFO @ 1250621078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 32120253732572783145720024467478881110219056097285435805280845122248102975795 77
UVM_INFO @ 334251144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 101385242597176292093886014124859506228136520161407194717479752593022830119528 83
UVM_INFO @ 2270424684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 21704320276809669732722666904873494272853050214936644705974827188280565682275 409
UVM_INFO @ 1187448390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 93504212279364329588624195790749839769249204478733098612338680972921934313459 75
UVM_INFO @ 3543569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 100562796781206880303363335865676766807659266341743745170183590718653888186496 308
UVM_INFO @ 2394704677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1170) [gpio_common_vseq] Check failed (vseq_done) 28 test runs
gpio_stress_all_with_rand_reset 94490037997290980936970259002151051415553505861794043879647315875530303838603 251
UVM_INFO @ 451427981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 31387708690119075110248917230741647534437043501710824465458977251147469101021 80
UVM_INFO @ 5151095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 5697900516372902657963053742524207102188044346757740575548533534497214505735 83
UVM_INFO @ 269767116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 20951632502448191570620831358112953245358011047274024277931683261241866840761 80
UVM_INFO @ 24749425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 74202722467784252439576507328984458978162174950111703432010179120194556799074 80
UVM_INFO @ 20196901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 65029383810231603961321086414719573814540475964294851338741730469996289924281 99
UVM_INFO @ 155931178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 115514452666464587995552700222669670859228151591540312901318149886500321390373 221
UVM_INFO @ 1739524020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 51288532682234694507973984843978835720671328808891317434162056303770672688919 81
UVM_INFO @ 1002793938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 25239054329816304521189532135619989004746848475746988065229941567145271026217 431
UVM_INFO @ 2277498085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 16175498542553044531517816086268369579153910165849996863446563964102951463093 82
UVM_INFO @ 731993967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 42856151594340831978016320256109755409736496365539423530822365018213900891236 80
UVM_INFO @ 1225446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 39100198504809004275397773118336736256105115342547327254417592240647088367582 82
UVM_INFO @ 6845848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 79781474186513721117887252806069824324101481734099571791374475089449147627024 80
UVM_INFO @ 20691001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 107576516548287946184307734955139080674035053507920390711854106876258602001144 139
UVM_INFO @ 477002310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 99543022881127932759002555049949984681271528140651591951464964275603209967409 80
UVM_INFO @ 13577662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 90823300503758442558937222085158049425804975550320810369726013951845640695247 80
UVM_INFO @ 20098071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 9252970812265461262865054965594488679052053514390150505339054754577141434310 84
UVM_INFO @ 1673006240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 81641321791380487157570764279824345089808866596467511324486123196854199216236 80
UVM_INFO @ 5579290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 32151473846364286901995114610041446084250182856411778647610435707603004972437 80
UVM_INFO @ 6120862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 77583629467177362763426815046831299393808423304143939305382730167828882051396 80
UVM_INFO @ 1574622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 93805649462918389788119261441270206130571012911167108383012079421137186700419 80
UVM_INFO @ 5167463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 87381119563829115345247778306027535012081381016020141230781633721731932605711 81
UVM_INFO @ 5887311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 37064392185907335795579725465398562182300878660752485300333035616634460742456 81
UVM_INFO @ 11932304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 64599325190024701843545781996135946037708699483069609136328317891100658270968 80
UVM_INFO @ 7612218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 292402599337686562719976415200088524056740012614479148254556854357495160426 80
UVM_INFO @ 5585763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 49064574154542370260610260523233522650187021471836616341534774473996064747749 98
UVM_INFO @ 2324176340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 24964453800979549925444737091644962473642680483777644196064878506643087468185 252
UVM_INFO @ 873878602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 108456288135809463694952347540565003007456282415689041289500530182468200471268 81
UVM_INFO @ 542694534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL sequencer [SEQDEFPRI] Sequence parent_sequence has illegal priority: -* 22 test runs
gpio_stress_all_with_rand_reset 4444072060809784346509535297591435152169600232010986172411363010785973305042 78
UVM_INFO @ 92291260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 111888192264036100334285284051634872053767749812108595536991669367660467569358 78
UVM_INFO @ 60619691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 82806813479259979500176981029932089238515517218362784264137594283761819066053 81
UVM_INFO @ 285103516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 103881517644016452716739966023230597059927432716371619973193784715884705804466 78
UVM_INFO @ 174676800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 59892705826884563704420315238820934703548684336390384768353406700572189920611 137
UVM_INFO @ 319773718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 38900032845157681748178812073293002696766375196787726425180485883899160970520 78
UVM_INFO @ 12155431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 24481800835282017375089025323719876245412589063274985470655035291036326786858 283
UVM_INFO @ 476022484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 10953423117514359309821561745815733710448996603411559510757058063310318096863 191
UVM_INFO @ 290464401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 17495160443179552299235334497015427829204133103531303735349039517970346225202 78
UVM_INFO @ 265923659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 20975882086348265125414459926868357230214733942548068908785840358660784787428 79
UVM_INFO @ 1931416593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 102013562752879031631961606157876832781455967859307236276836156773902814099649 78
UVM_INFO @ 86449960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 56597741489495934285512852618052430479680732167349960238697494724984771593300 78
UVM_INFO @ 325899749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 49742168929068251368409914036189922436753777678651247432582875466405330611050 80
UVM_INFO @ 3216798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 75163637274296304936951853805771841338319348563829626999563281451162610651660 81
UVM_INFO @ 4497216254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 17926555688263770641030210627987211752117085813413159409256492357987213979443 78
UVM_INFO @ 628190545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 47816755713886147725582055004732549063151063195226881762184426376431516976956 78
UVM_INFO @ 196188212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 6995839024415945531016429079392938408272790823186934742882430497790118372696 79
UVM_INFO @ 170852055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 91397152610814474701586678781441639482535351262931707975936358319004364920620 78
UVM_INFO @ 2005666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 88645301850123321102995214863160862808598600180932223543870674072930784260124 81
UVM_INFO @ 695936171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 43875122227050000570290632114273147906710593136165482890421410377530730911511 181
UVM_INFO @ 62964482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 53301612075790129803065295903789548326541743835669382922444922986336582312539 83
UVM_INFO @ 566215582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 16667270418161657980727618872289150224972081282949426696991503058928637532764 78
UVM_INFO @ 28271143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---