Simulation Results: hmac

 
09/05/2026 22:36:56 DVSim: v1.34.0 sha: f3ee88d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 99.04 %
  • code
  • 99.32 %
  • assert
  • 97.80 %
  • func
  • 100.00 %
  • line
  • 99.90 %
  • branch
  • 99.83 %
  • cond
  • 96.85 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 13.200s 2226.739us 10 10 100.00
csr_hw_reset 5 5 100.00
hmac_csr_hw_reset 1.300s 22.703us 5 5 100.00
csr_rw 20 20 100.00
hmac_csr_rw 1.310s 118.443us 20 20 100.00
csr_bit_bash 5 5 100.00
hmac_csr_bit_bash 14.440s 1051.399us 5 5 100.00
csr_aliasing 5 5 100.00
hmac_csr_aliasing 7.890s 1624.910us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
hmac_csr_mem_rw_with_rand_reset 659.900s 58673.079us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
hmac_csr_rw 1.310s 118.443us 20 20 100.00
hmac_csr_aliasing 7.890s 1624.910us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 85.100s 1652.717us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 88.740s 6832.549us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 259.500s 25470.816us 30 30 100.00
hmac_test_sha384_vectors 537.110s 14573.178us 75 75 100.00
hmac_test_sha512_vectors 517.850s 14689.976us 75 75 100.00
hmac_test_hmac256_vectors 14.440s 3221.690us 50 50 100.00
hmac_test_hmac384_vectors 14.780s 714.570us 60 60 100.00
hmac_test_hmac512_vectors 19.010s 1499.463us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 33.360s 2811.040us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 1046.380s 11032.345us 10 10 100.00
error 10 10 100.00
hmac_error 85.260s 5612.428us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 124.170s 23656.215us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 13.200s 2226.739us 10 10 100.00
hmac_long_msg 85.100s 1652.717us 10 10 100.00
hmac_back_pressure 88.740s 6832.549us 25 25 100.00
hmac_datapath_stress 1046.380s 11032.345us 10 10 100.00
hmac_burst_wr 33.360s 2811.040us 50 50 100.00
hmac_stress_all 2371.230s 106723.309us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 13.200s 2226.739us 10 10 100.00
hmac_long_msg 85.100s 1652.717us 10 10 100.00
hmac_back_pressure 88.740s 6832.549us 25 25 100.00
hmac_datapath_stress 1046.380s 11032.345us 10 10 100.00
hmac_wipe_secret 124.170s 23656.215us 10 10 100.00
hmac_test_sha256_vectors 259.500s 25470.816us 30 30 100.00
hmac_test_sha384_vectors 537.110s 14573.178us 75 75 100.00
hmac_test_sha512_vectors 517.850s 14689.976us 75 75 100.00
hmac_test_hmac256_vectors 14.440s 3221.690us 50 50 100.00
hmac_test_hmac384_vectors 14.780s 714.570us 60 60 100.00
hmac_test_hmac512_vectors 19.010s 1499.463us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 13.200s 2226.739us 10 10 100.00
hmac_long_msg 85.100s 1652.717us 10 10 100.00
hmac_back_pressure 88.740s 6832.549us 25 25 100.00
hmac_datapath_stress 1046.380s 11032.345us 10 10 100.00
hmac_burst_wr 33.360s 2811.040us 50 50 100.00
hmac_error 85.260s 5612.428us 10 10 100.00
hmac_wipe_secret 124.170s 23656.215us 10 10 100.00
hmac_test_sha256_vectors 259.500s 25470.816us 30 30 100.00
hmac_test_sha384_vectors 537.110s 14573.178us 75 75 100.00
hmac_test_sha512_vectors 517.850s 14689.976us 75 75 100.00
hmac_test_hmac256_vectors 14.440s 3221.690us 50 50 100.00
hmac_test_hmac384_vectors 14.780s 714.570us 60 60 100.00
hmac_test_hmac512_vectors 19.010s 1499.463us 75 75 100.00
hmac_stress_all 2371.230s 106723.309us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 2371.230s 106723.309us 50 50 100.00
alert_test 50 50 100.00
hmac_alert_test 0.950s 47.639us 50 50 100.00
intr_test 50 50 100.00
hmac_intr_test 0.980s 34.970us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
hmac_tl_errors 4.710s 798.337us 20 20 100.00
tl_d_illegal_access 20 20 100.00
hmac_tl_errors 4.710s 798.337us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
hmac_csr_hw_reset 1.300s 22.703us 5 5 100.00
hmac_csr_rw 1.310s 118.443us 20 20 100.00
hmac_csr_aliasing 7.890s 1624.910us 5 5 100.00
hmac_same_csr_outstanding 2.900s 134.181us 20 20 100.00
tl_d_partial_access 50 50 100.00
hmac_csr_hw_reset 1.300s 22.703us 5 5 100.00
hmac_csr_rw 1.310s 118.443us 20 20 100.00
hmac_csr_aliasing 7.890s 1624.910us 5 5 100.00
hmac_same_csr_outstanding 2.900s 134.181us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
hmac_sec_cm 1.340s 297.714us 5 5 100.00
hmac_tl_intg_err 4.450s 1052.679us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
hmac_tl_intg_err 4.450s 1052.679us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 13.200s 2226.739us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 8.010s 327.208us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 960.390s 406676.023us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 0.840s 86.914us 1 1 100.00